BRISC-V: An Open-Source Architecture Design Space Exploration Toolbox
Sahan Bandara, Alan Ehret, Donato Kava, Michel A. Kinsy

TL;DR
BRISC-V is an open-source, modular platform for designing, exploring, and simulating RISC-V based architectures at RTL level, supporting rapid customization and multi-core system development.
Contribution
It introduces a highly-parameterized, modular RTL platform for RISC-V architecture exploration, enabling fast design space exploration and easy modifications.
Findings
Supports a wide range of RISC-V architectures
Enables quick instantiation of multi-core systems
Provides tools for software development and simulation
Abstract
In this work, we introduce a platform for register-transfer level (RTL) architecture design space exploration. The platform is an open-source, parameterized, synthesizable set of RTL modules for designing RISC-V based single and multi-core architecture systems. The platform is designed with a high degree of modularity. It provides highly-parameterized, composable RTL modules for fast and accurate exploration of different RISC-V based core complexities, multi-level caching and memory organizations, system topologies, router architectures, and routing schemes. The platform can be used for both RTL simulation and FPGA based emulation. The hardware modules are implemented in synthesizable Verilog using no vendor-specific blocks. The platform includes a RISC-V compiler toolchain to assist in developing software for the cores, a web-based system configuration graphical user interface (GUI)…
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