Cyclic Sequence Generators as Program Counters for High-Speed FPGA-based Processors

TL;DR

This paper evaluates FPGA-based program counters, showing that Feedback Shift Register (FSR) counters outperform traditional radix-2 counters in speed and resource efficiency, especially in high-speed processor designs.

Contribution

It introduces FSR-based program counters as a high-speed alternative to radix-2 counters, with hybrid solutions addressing cache-coherency issues.

Findings

FSR counters have constant time scaling with bit-width.

High-speed FPGA processors benefit from FSR counters in frequency and resource use.

Hybrid counters mitigate cache-coherency issues.

Abstract

This paper compares the performance of conventional radix-2 program counters with program counters based on Feedback Shift Registers (FSRs), a class of cyclic sequence generator. FSR counters have constant time scaling with bit-width, $N$, whereas FPGA-based radix-2 counters typically have $O(N)$ time-complexity due to the carry-chain. Program counter performance is measured by synthesis of standalone counter circuits, as well as synthesis of three FPGA-based processor designs modified to incorporate FSR program counters. Hybrid counters, combining both an FSR and a radix-2 counter, are presented as a solution to the potential cache-coherency issues of FSR program counters. Results show that high-speed processor designs benefit more from FSR program counters, allowing both greater operating frequency and the use of fewer logic resources.