Analog circuits for mixed-signal neuromorphic computing architectures in 28 nm FD-SOI technology

TL;DR

This paper introduces compact, energy-efficient analog circuits for neuromorphic computing in 28 nm FD-SOI technology, addressing design challenges and demonstrating their effectiveness through simulation results.

Contribution

It presents novel sub-threshold analog synapse and neuron circuits optimized for advanced process technology, enabling large-scale, energy-efficient neuromorphic systems.

Findings

Demonstrated circuit simulation results for the proposed designs

Showed effectiveness in both low-frequency and high-frequency neuromorphic applications

Addressed channel leakage current minimization in analog circuit design

Abstract

Developing mixed-signal analog-digital neuromorphic circuits in advanced scaled processes poses significant design challenges. We present compact and energy efficient sub-threshold analog synapse and neuron circuits, optimized for a 28 nm FD-SOI process, to implement massively parallel large-scale neuromorphic computing systems. We describe the techniques used for maximizing density with mixed-mode analog/digital synaptic weight configurations, and the methods adopted for minimizing the effect of channel leakage current, in order to implement efficient analog computation based on pA-nA small currents. We present circuit simulation results, based on a new chip that has been recently taped out, to demonstrate how the circuits can be useful for both low-frequency operation in systems that need to interact with the environment in real-time, and for high-frequency operation for fast data processing in different types of spiking neural network architectures.