Scaling mixed-signal neuromorphic processors to 28 nm FD-SOI technologies

TL;DR

This paper analyzes the challenges and solutions for scaling mixed-signal neuromorphic processors to 28 nm FD-SOI technology, addressing analog design issues, asynchronous digital design, and memory integration.

Contribution

It presents a comprehensive analysis of scaling neuromorphic processors to 28 nm FD-SOI, including analog/digital circuit simulations, asynchronous routing validation, and memory resource implementation.

Findings

Successful simulation of biologically plausible neuron responses

Validation of asynchronous routing in multi-core architecture

Feasibility of integrating advanced RRAM devices for higher density

Abstract

As processes continue to scale aggressively, the design of deep sub-micron, mixed-signal design is becoming more and more challenging. In this paper we present an analysis of scaling multi-core mixed-signal neuromorphic processors to advanced 28 nm FD-SOI nodes. We address analog design issues which arise from the use of advanced process, including the problem of large leakage currents and device mismatch, and asynchronous digital design issues. We present the outcome of Monte Carlo Analysis and circuit simulations of neuromorphic sub threshold analog/digital neuron circuits which reproduce biologically plausible responses. We describe the AER used to implement PCHB based asynchronous QDI routing processes in multi-core neuromorphic architectures and validate their operation via circuit simulation results. Finally we describe the implementation of custom 28 nm CAM based memory resources utilized in these multi-core neuromorphic processor and discuss the possibility of increasing density by using advanced RRAM devices integrated in the 28 nm Fully-Depleted Silicon on Insulator (FD-SOI) process.