# A clock-less ultra-low power bit-serial LVDS link for Address-Event   multi-chip systems

**Authors:** Ning Qiao, Giacomo Indiveri

arXiv: 1908.06532 · 2019-08-20

## TL;DR

This paper introduces a clock-less, ultra-low power, asynchronous LVDS link optimized for high-speed inter-chip communication of neuromorphic systems, achieving high data rates with minimal power consumption.

## Contribution

It proposes a novel clock-less LVDS architecture using Level-Encoded Dual-Rail encoding and token-ring architecture, eliminating traditional power-hungry clock recovery modules.

## Key findings

- Achieves 35.7 million events per second at 1.5 Gbps
- Power consumption drops below 1 microamp at low event rates
- Total silicon area is 0.14 mm^2

## Abstract

We present a power efficient clock-less fully asynchronous bit-serial Low Voltage Differential Signaling (LVDS) link with event-driven instant wake-up and self-sleep features, optimized for high speed inter-chip communication of asynchronous address-events between neuromorphic chips. The proposed LVDS link makes use of the Level-Encoded Dual-Rail (LEDR) representation and a token-ring architecture to encode and transmit data, avoiding the use of conventional large ClockData Recovery (CDR) modules with power-hungry DLL or PLL circuits. We implemented the LVDS circuits in a device fabricated with a standard 0.18 um CMOS process. The total silicon area used for such block is of 0.14 mm^2. We present experimental measurement results to demonstrate that, with a bit rate of 1.5 Gbps and an event width of 32-bit, the proposed LVDS link can achieve transmission event rates of 35.7 M Events/second with current consumption of 19.3 mA and 3.57 mA for receiver and transmitter blocks, respectively. Given the clock-less and instant on/off design choices made, the power consumption of the whole link depends linearly on the data transmission rate. We show that the current consumption can go down to sub-uA for low event rates (e.g., <1k Events/second), with a floor of 80 nA for transmitter and 42 nA for receiver, determined mainly by static off-leakage currents.

## Full text

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## Figures

16 figures with captions in the complete paper: https://tomesphere.com/paper/1908.06532/full.md

## References

19 references — full list in the complete paper: https://tomesphere.com/paper/1908.06532/full.md

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Source: https://tomesphere.com/paper/1908.06532