# Near Data Acceleration with Concurrent Host Access

## TL;DR

This paper presents a new memory architecture that enables efficient near-data acceleration with concurrent host access, addressing key challenges in memory sharing, locality, and interface support to improve performance and power efficiency.

## Contribution

It introduces novel techniques for mitigating interference, reducing turnaround overhead, and supporting diverse memory interfaces in NDA-enabled memory systems.

## Key findings

- Effective concurrent access demonstrated with microbenchmarks
- Improved performance for stochastic variance-reduced gradient (SVRG) algorithm
- Memory layout and interface strategies enhance NDA and host collaboration

## Abstract

Near-data accelerators (NDAs) that are integrated with main memory have the potential for significant power and performance benefits. Fully realizing these benefits requires the large available memory capacity to be shared between the host and the NDAs in a way that permits both regular memory access by some applications and accelerating others with an NDA, avoids copying data, enables collaborative processing, and simultaneously offers high performance for both host and NDA. We identify and solve new challenges in this context: mitigating row-locality interference from host to NDAs, reducing read/write-turnaround overhead caused by fine-grain interleaving of host and NDA requests, architecting a memory layout that supports the locality required for NDAs and sophisticated address interleaving for host performance, and supporting both packetized and traditional memory interfaces. We demonstrate our approach in a simulated system that consists of a multi-core CPU and NDA-enabled DDR4 memory modules. We show that our mechanisms enable effective and efficient concurrent access using a set of microbenchmarks, and then demonstrate the potential of the system for the important stochastic variance-reduced gradient (SVRG) algorithm.