Covert Computation in Self-Assembled Circuits

TL;DR

This paper introduces the concept of covert computation in self-assembled circuits, enabling hidden inputs and computational processes within tile assembly models, with implications for privacy and cryptography.

Contribution

It defines the problem of covert computation in tile self-assembly, designs basic covert logic gates, and demonstrates the coNP-completeness of a key verification problem.

Findings

Covert logic gates can simulate any circuit in the model.

Covert computation is feasible within the growth-only aTAM with negative interactions.

Verification of unique assembly is coNP-complete.

Abstract

Traditionally, computation within self-assembly models is hard to conceal because the self-assembly process generates a crystalline assembly whose computational history is inherently part of the structure itself. With no way to remove information from the computation, this computational model offers a unique problem: how can computational input and computation be hidden while still computing and reporting the final output? Designing such systems is inherently motivated by privacy concerns in biomedical computing and applications in cryptography. In this paper we propose the problem of performing ``covert computation'' within tile self-assembly that seeks to design self-assembly systems that ``conceal'' both the input and computational history of performed computations. We achieve these results within the growth-only restricted abstract Tile Assembly Model (aTAM) with positive and negative interactions. We show that general-case covert computation is possible by implementing a set of basic covert logic gates capable of simulating any circuit (functionally complete). To further motivate the study of covert computation, we apply our new framework to resolve an outstanding complexity question; we use our covert circuitry to show that the unique assembly verification problem within the growth-only aTAM with negative interactions is coNP-complete.

Tables

Table 1. Table 1 : The complexity of Unique Assembly Verification in the aTAM in relation to negative glues. | A | 𝐴 |A| refers to the size of an assembly and | T | 𝑇 |T| is the number of tile types.

Model	Negative Glues	Detachment	Complexity	Theorem
aTAM	No	No	$O\left({\left|A\right|}^2+\left|A\right|\left|T\right|\right)$	Thm. 3.2 in [1]
aTAM	Yes	No	coNP-complete	Thm. 2
aTAM	Yes	Yes	Undecidable	[11]

Full text

In this paper we propose the problem of performing “covert computation” within tile self-assembly that seeks to design self-assembly systems that “conceal” both the input and computational history of performed computations. We achieve these results within the growth-only restricted abstract tile assembly model (aTAM) with positive and negative interactions. We show that general-case covert computation is possible by implementing a set of basic covert logic gates capable of simulating any circuit (functionally complete). To further motivate the study of covert computation, we apply our new framework to resolve an outstanding complexity question; we use our covert circuitry to show that the unique assembly verification problem within the growth-only aTAM with negative interactions is coNP-complete.

Department of Computer Science

University of Texas - Rio Grande Valley

{angel.cantu01, austin.luchsinger01, robert.schweller, timothy.wylie}@utrgv.edu

1 Introduction

Since the discovery of DNA over half a century ago, humans have been continually working to understand and harness the vast amount of information it contains. The Human Genome Project [19], which began in 1990 and took a decade, was the first major attempt to fully sequence the human genome. In the years since, sequencing has become extremely cheap and easy, and our ability to manipulate DNA has emerged as a central tool for many applications related to nanotechnology and biomedical engineering.

Although this progress has many benefits, as we learn more about the information, we also must be careful with the shared data. There are databases of anonymous DNA sequences, which can sometimes be deanonymized with only small amounts of information such as a surname [16], or by reconstructing physical features from the DNA [8]. In order to address these issues, there has been work on cryptographic schemes aimed at obscuring results related to DNA or the input/output [9, 13, 17, 30].

In this work we take the first steps in addressing some of these issues within self-assembling systems by proposing a new style of computation termed covert computation with important motivations for private biomedical computing and cryptography. Self-assembly is the process by which systems of simple objects autonomously organize themselves through local interactions into larger, more complex objects. Understanding how to design and efficiently program molecular self-assembly systems is fundamental for the future of nanotechnology. The abstract Tile Self-Assembly Model (aTAM) [10, 21], motivated by a DNA implementaiton [14], has become the premiere model for the study of the computational power of self-assembling systems. In the aTAM, system monomers are modeled by four-sided Wang tiles which randomly combine and attach if the respective bonding domains on tile edges are sufficiently strong. The aTAM is known to be computationally universal [29] and intrinsically universal [12].

Covert Computation. As a computational model, tile self-assembly differs from traditional models of computation in that computational steps are defined by permanently placing particular tile types at specific locations in geometric space. A history of each computational step is thereby recorded in the final assembled structure. This presents a unique problem to this type of computation: is it possible to conceal the input and history of a computation within the final assembly while still computing and reporting the output of the computation? Concealing the computational histories of the self-assembly process in this way requires designing a computational system which encodes computational steps in the order of tile placement, rather than the type and location of tile placements. We use the term covert111It is important to note that the term covert has specific meaning in cryptography which does not apply here. to describe this concealment of inputs and computational histories. This method of computing is different than previous tile self-assembly computing methods and requires novel techniques.

Also, while the reader may notice many parallels between our work and traditional secure multiparty computation [6], it should be made clear that our main result is the secure computation of a function with only a single party. The challenges presented above make this an interesting problem for tile self-assembly.

Motivation. The concept of covert computation within self-assembly has many potential applications. We briefly outline a few biomedical computing applications. Consider a set of diagnostic tiles sent to a patient as a droplet of DNA to which the patient adds some biological input such as a blood sample. From this the diagnostic system could compute some desired function that outputs specific diagnostic statistics. The patient sends the combined product to a medical facility for interpretation. With covert computation, only the results can be read by the lab and the user’s biological input is obscured ensuring privacy.

Another potential use involves implementing a cryptography system within a molecular computing framework. The ability to covertly compute allows users to provide a personal key input that may be combined with a publicly available covert system where the combination verifies some computable property of the input key without revealing any additional details of the key. This style of cryptographic scheme fits well when the input keys are biological based inputs.

A final potential biological application might be engineering a system for unlocking key biological properties within bio-engineered crops. For example, by releasing a hidden “key” input, covert computation might allow a field of crops to become fertile. A company owning the patent on this type of activation might desire the security of ensuring that the release key cannot be deciphered from the activated crop based on a covert molecular computation.

The final motivation of covert computation is within algorithmic self-assembly. We believe the concept of covert computation is fundamental and hope that our novel design techniques will be applicable to a number of future problems in the area. As evidence towards this, we apply our techniques to resolve the complexity of the fundamental question of verifying whether a tile system uniquely assembles a given assembly within the growth-only negative-glue aTAM.

Contributions. After formally defining the concept of covert computation in tile self-assembly, we implement several covert logic gates within the negative-glue growth-only abstract Tile Assembly Model (this growth-only restriction to negative glues has been seen in the 2HAM [5], and negative glues in tile assembly have received extensive study [4, 11, 20, 23, 22, 24, 25]), and show these gates may be combined to create general circuits, thereby showing that general covert computation is possible. Finally, we apply our techniques and framework to address the fundamental problem of deciding if a negative-glue aTAM system uniquely produces a given assembly. We show this problem is coNP-complete. Table 1 outlines how our result compares to what was previously known about Unique Assembly Verification in the aTAM.

This work is an extension of a paper originally published in [3]. We have included a lot more detail as well as additional examples and gadgets. There was also a small issue with the NAND gadget related to backfilling which has been corrected. The backfill stop gadget was also added, which allows backfilling to begin along a wire for a cleaner construction with the FANOUT and at the output.

2 Definitions

We begin with an overview of the abstract Tile-Assembly Model (aTAM) and then give the new definitions introducing covert computation. Due to the extensive use of the aTAM in the literature, we only give a high-level overview of the aTAM.

2.1 Abstract Tile Assembly Model

Figure 1 gives a high-level overview of the models with a couple of example systems. Essentially, we have non-rotating square tiles that have a glue label on each edge. The tile with its labels is a tile type. The tile set is all the tile types. A glue function determines the strength of matching glue labels. An assembly is a single tile or a finite set of tiles that have combined via the glues. If the combined strength of the glue labels of a single attaching tile to an assembly is greater than or equal to the temperature $\tau$, the tile may attach. A producible assembly is any assembly that might be achieved by beginning with the seed (the specified starting assembly) and attaching tiles. A producible assembly is further said to be terminal if no further tile attachment is possible. A tile system is said to uniquely produce a (terminal) assembly $A$ if all producible assemblies will eventually grow into $A$. A tile system is formally represented as an ordered triplet $\Gamma=(T,S,\tau)$ representing the tile set, seed assembly, and temperature parameter of the system respectively.

In a standard aTAM system, all glues are positive integral values, but here we look at the negative aTAM where the glues may be negative/repulsive. Such repulsive forces may be used to block the attachment of tiles despite the presence of strong attractive glues. Moreover, the inclusion of repulsive forces may yield unstable producible assemblies where a subassembly could detach because it no longer has enough binding strength. While this type of detachment has been studied in the literature [11, 25], we avoid this feature in this work as its inclusion drastically changes the complexity of the model by making most types of verification problems undecidable, and may require more sophisticated techniques for experimental implementation. Thus, we consider a system to be a valid growth-only system if all producible assemblies are $\tau$-stable. In this paper we restrict our consideration to valid growth-only systems.

2.2 Formal Definitions

Tiles. Let $\Pi$ be an alphabet of symbols called the glue types. A tile is a finite edge polygon with some finite subset of border points each assigned a glue type from $\Pi$. Each glue type $g\in\Pi$ also has some integer strength $str(g)$. Here, we consider unit square tiles of the same orientation with at most one glue type per face, and the location to be the center of the tile located at integer coordinates.

Assemblies. An assembly $A$ is a finite set of tiles whose interiors do not overlap. If each tile in $A$ is a translation of some tile in a set of tiles $T$, we say that $A$ is an assembly over tile set $T$. For a given assembly $A$, define the bond graph $G_{A}$ to be the weighted graph in which each element of $A$ is a vertex, and the weight of an edge between two tiles is the strength of the overlapping matching glue points between the two tiles. Only overlapping glues of the same type contribute a non-zero weight, whereas overlapping, non-equal glues contribute zero weight to the bond graph. The property that only equal glue types interact with each other is referred to as the diagonal glue function property and is perhaps more feasible than more general glue functions for experimental implementation (see [7] for the theoretical impact of relaxing this constraint). An assembly $A$ is said to be $\tau$-stable for an integer $\tau$ if the min-cut of $G_{A}$ has weight at least $\tau$.

Tile Attachment. Given a tile $t$, an integer $\tau$, and an assembly $A$, we say that $t$ may attach to $A$ at temperature $\tau$ to form $A^{\prime}$ if there exists a translation $t^{\prime}$ of $t$ such that $A^{\prime}=A\cup\{t^{\prime}\}$, and the sum of newly bonded glues between $t^{\prime}$ and $A$ meets or exceeds $\tau$. For a tile set $T$ we use notation $A\rightarrow_{T,\tau}A^{\prime}$ to denote there exists some $t\in T$ that may attach to $A$ to form $A^{\prime}$ at temperature $\tau$. When $T$ and $\tau$ are implied, we simply say $A\rightarrow A^{\prime}$. Further, we say that $A\rightarrow^{*}A^{\prime}$ if either $A=A^{\prime}$, or there exists a finite sequence of assemblies $\langle A_{1}\ldots A_{k}\rangle$ such that $A\rightarrow A_{1}\rightarrow\ldots\rightarrow A_{k}\rightarrow A^{\prime}$.

Tile Systems. A tile system $\Gamma=(T,S,\tau)$ is an ordered triplet consisting of a set of tiles $T$ called the system’s tile set, a $\tau$-stable assembly $S$ called the system’s seed assembly, and a positive integer $\tau$ referred to as the system’s temperature. A tile system $\Gamma=(T,S,\tau)$ has an associated set of producible assemblies, $\texttt{PROD}_{\Gamma}$, which define what assemblies can grow from the initial seed $S$ by any sequence of temperature $\tau$ tile attachments from $T$. Formally, $S\in\texttt{PROD}_{\Gamma}$ is a base case producible assembly. Further, for every $A\in\texttt{PROD}_{\Gamma}$, if $A\rightarrow_{T,\tau}A^{\prime}$, then $A^{\prime}\in\texttt{PROD}_{\Gamma}$. That is, assembly $S$ is producible, and for every producible assembly $A$, if $A$ can grow into $A^{\prime}$, then $A^{\prime}$ is also producible. We further denote a producible assembly $A$ to be terminal if $A$ has no attachable tile from $T$ at temperature $\tau$. We say a system $\Gamma=(T,S,\tau)$ uniquely produces an assembly $A$ if all producible assemblies can grow into $A$ through some sequence of tile attachments. More formally, $\Gamma$ uniquely produces an assembly $A\in\texttt{PROD}_{\Gamma}$ if for every $A^{\prime}\in\texttt{PROD}_{\Gamma}$ it is the case that $A^{\prime}\rightarrow^{*}A$. Systems that uniquely produce one assembly are said to be deterministic.

Finally, we consider a system to be a valid growth-only system if all assemblies in $\texttt{PROD}_{\Gamma}$ are $\tau$-stable. The existence of negative strength glues allows for the possibility that unstable assemblies are produced.

2.3 Covert Computation

Here, we provide formal definitions for computing a function with a tile system, and the further requirement for covert computation of a function. Our formulation of computing functions is based on that of [18] but modified to allow for each bit to be represented by a sub-assembly potentially larger than a single tile.

Informally, a Tile Assembly Computer (TAC) for a function $f$ consists of a set of tiles, along with a format for both input and output. The input format is a specification for how to build an input seed for the system that encodes the desired input bit-string for function $f$. We require that each bit of the input be mapped to one of two assemblies for the respective bit position: a sub-assembly representing “0”, or a sub-assembly representing “1”. The input seed for the entire string is the union of all these sub-assemblies. This seed, along with the tile set of the TAC, forms a tile system. The output of the computation is the final terminal assembly this system builds. To interpret what bit-string is represented by the output, a second output format specifies a pair of sub-assemblies for each bit. The bit-string represented by the union of these subassemblies within the constructed assembly is the output of the system.

For a TAC to covertly compute $f$, the TAC must compute $f$ and produce a unique assembly for each possible output of $f$. We note that our formulation for providing input and interpreting output is quite rigid and may prohibit more exotic forms of computation. We acknowledge this, but caution that any formulation must take care to prevent “cheating” that could allow the output of a function to be partially or completely encoded within the input, for example. To prevent this, some type of uniformity constraint, similar to what is considered in circuit complexity [28], should be enforced. We now provide the formal definitions of function computing and covert computation.

Input/Output Templates. An $n$-bit input/output template over tile set $T$ is a sequence of ordered pairs of assemblies over $T$: $A=(A_{0,0},A_{0,1}),$ $\ldots,(A_{n-1,0},$ $A_{n-1,1})$. For a given $n$-bit string $b=b_{0},\ldots,b_{n-1}$ and $n$-bit input/output template $A$, the representation of $b$ with respect to $A$ is the assembly $A(b)=\bigcup_{i}A_{i,b_{i}}$. A template is valid for a temperature $\tau$ if this union never contains overlaps for any choice of $b$, and is always $\tau$-stable. An assembly $B\supseteq A(b)$, which contains $A(b)$ as a subassembly, is said to represent $b$ as long as $A(d)\nsubseteq B$ for any $d\neq b$.

Function Computing Problem. A tile assembly computer (TAC) is an ordered quadruple $\Im=(T,I,O,\tau)$ where $T$ is a tile set, $I$ is an $n$-bit input template, and $O$ is a $k$-bit output template. A TAC is said to compute function $f:\mathbb{Z}_{2}^{n}\rightarrow\mathbb{Z}_{2}^{k}$ if for any $b\in\mathbb{Z}_{2}^{n}$ and $c\in\mathbb{Z}_{2}^{k}$ such that $f(b)=c$, then the tile system $\Gamma_{\Im,b}=(T,I(b),\tau)$ uniquely assembles a set of assemblies at temperature $\tau$ which all represent $c$ with respect to template $O$.

Covert Computation. A TAC covertly computes a function $f(b)=c$ if 1) it computes $f$, and 2) for each $c$, there exists a unique assembly $A_{c}$ such that for all $b$, where $f(b)=c$, the system $\Gamma_{\Im,b}=(T,I(b),\tau)$ uniquely produces $A_{c}$. In other words, $A_{c}$ is determined by $c$, and every $b$ where $f(b)=c$ has the exact same final assemby.

3 Covert Circuits

Here we cover the machinery for making covert gadgets and the covert gadgets needed for functional completeness in circuits based on a dual-rail logic implementation: variables, wires, fanouts, and NANDs. We cover a NOT gate as a primitive used in the NAND construction. Traditionally, a crossover is also given, and we discuss why this is unnecessary in Section 4. For simplicity, we give some other common gates in Section 5.

Some Conventions. All solid lines through two neighboring tiles indicate strength-2 glues between them. The arrows indicate the build order (which may branch). Blue single glues are strength 1, and red are strength -1. Following the variable gadget (Figure 3(b)), all variables have a true and false path adjacent to each other (dual-rail logic), but only one may be traversed at a time until the next gadget. The true value is always to the left or on top of the false value, and for most gadgets, the true input is colored grey while the false input is colored green. Once a variable wire, true or false, reaches the next gadget, the unused variable wire is backfilled so that both wires are present. This is a key concept used in all constructions and is further explained in Figure 2.

3.1 Variables and Wires

A variable in our system is represented by two lines of connected tiles where only one exists at a time when the wire is in use (dual rail). Figure 3(a) shows an example of the possible input seeds on 2-bits used in a half-adder. Figure 3(b) demonstrates how the variables might be set nondeterministically, although generally the specific bits desired would already be attached as part of the input seed (as in Figure 3(a)). Each variable $v_{i}$ has a sequence of tiles $t_{i}$ representing a true setting and $f_{i}$ a false setting. The first tiles have a negative glue of strength $-1$ meaning only the $t_{i}$ or the $f_{i}$ tile can attach. The other shown glues are strength 2. Once the variable is set, the setting travels to the gadget as a wire.

The variable setup in Figure 3(b) is used in one of two ways: In the case of providing an input to a covert computation, this variable setup defines the input template for the computation, with the seed for a given binary input being the seed assembly with either a true or false tile (but not both) placed at each bit position. An example system (a half-adder) with a big seed input is shown in Figure 13. Alternatively, the seed begins as a single seed tile that nondeterministically creates a valid input over all possible $n$-bit inputs. This approach is used in Section 4 to show coNP-completeness for unique assembly verification.

3.2 Backfill Stops

Figure 4(a) shows a backfill stop, or simply a backstop. This continues a signal, but also backfills the other wire up to this gadget. This ensures that everything up to this gadget has the signals needed to begin backfilling. It has the following properties.

• 1.

If $t_{i}^{in}$ enters, then only $t_{i}^{out}$ leaves, and $f_{i}^{in}$ is also populated. Since $t_{i}^{out}$ attaches the tile with the $n_{3}$ glue, the tile going to $f_{i}^{out}$ can not attach. However, the $h_{1},h_{3}$ glues allows a tile from $f_{i}^{in}$ to attach cooperatively, which allows backfilling of the wire. The $n_{2}$ glue prevents the wire from attaching another tile towards the output though.

• 2.

If $f_{i}^{in}$ enters, then only $f_{i}^{out}$ leaves, and $t_{i}^{in}$ is also populated. Since $f_{i}^{out}$ attaches the tile with the $n_{3}$ glue, the tile going to $t_{i}^{out}$ can not attach. However, the $h_{1},h_{2}$ glues allows a tile from $t_{i}^{in}$ to attach cooperatively, which allows backfilling of the wire. The $n_{1}$ glue prevents the wire from attaching another tile towards the output though.

3.3 Logic Diodes

Figure 4(b) shows what we refer to as a logic diode, and prevents timing issues. These appear in every gadget and serve two purposes: if backfilling, this stops the filling at the gadget level so it does not backfill a wire that has not been set, and second it ensures that a gadget must have input from the wire. All shown glues are strength 1 and the lines are strength 2. This gadget is important for later constructions. It must have these properties.

• 1.

If $t_{i}^{in}$ enters, then only $t_{i}^{out}$ leaves. This is guaranteed due to $h_{2},h_{3}$ cooperatively attaching the next tile. Without $f_{i}^{in}$ present, the only tile which could attach is the cooperatively-placed tile from $t_{i}^{out}$.

• 2.

If $f_{i}^{in}$ enters, then only $f_{i}^{out}$ leaves. This is guaranteed due to $h_{4},h_{5}$ cooperatively attaching the next tile. Without $t_{i}^{in}$ present, the only tile which could attach is the cooperatively-placed tile from $f_{i}^{out}$.

• 3.

The $t_{i}^{in}$ wire will be backfilled if and only if $f_{i}^{in}$ enters. Without $f_{i}^{in}$ present, a backfilled false path will stop at the tile with $h_{2},h_{3}$. However, with $f_{i}^{in}$ present, the $h_{1},h_{2}$ tile can cooperatively attach and backfill the true wire.

• 4.

The $f_{i}^{in}$ wire will be backfilled if and only if $t_{i}^{in}$ enters. Without $t_{i}^{in}$ present, a backfilled false path will stop at the tile with $h_{4},h_{5}$. With $t_{i}^{in}$ present, the tile with $h_{1},h_{4}$ can cooperatively attach and backfill the false wire.

3.4 Covert NOT Gadget

The first covert gadget we introduce is a NOT gadget. This gadget displays some of the key insights needed for covert computation, such as how blocking with negative glue adds power to the system. The NOT gadget is also used as a submodule within our NAND gadget. The NOT gadget is shown in Figure 5(a), and Figure 5(b) is the NOT gadget with the logic diode added on the input to ensure no backfill happens unless the gadget has receieved input. In the NAND gadget, we also use the same structure as the NOT gadget, but with an additional negative glue. This is shown in Figure 5(c) and will be discussed when needed.

Given the variables and wires work as shown, the difficulty in a dual-rail NOT is that there must be at least one crossing tile that both the true and false paths place. This tile can be thought of as where the signals cross or switch. Figure 5(a) shows the basic NOT gadgets, and the tile shared by both paths is labelled $x$. The negative glues allow blocking around this tile so that only one path is possible once $x$ is placed.

The properties of the NOT gadget guarantee that it works correctly and that the gadget is covert (the gadget looks indistinguishable before the output regardless of the input), and that the backfill works correctly. Figure 6 discusses these elements and walks through how the true/false inputs block and crossover correctly. The figure does not show the logic diode though.

In verifying that the gadget works as intended, we must verify six properties. The first two conditions guarantee that the gadget works correctly. The second two conditions are needed along with the last two to guarantee the covertness of the gadget, i.e., the gadget looks indistinguishable before the output regardless of the input. The final two conditions also verify that the backfill from future gadgets will work correctly, and no trace of the build path will be evident.

• 1.

If $t_{i}^{in}$ enters a NOT gadget, it results in $f_{i}^{out}$ and not $t_{i}^{out}$. Figure 6(a) shows the gadget in this case with true input $t_{i}^{in}$ and output $f_{i}^{out}$. The true output can not place from tile $x$ due to the negative glues $n_{1}$ and $n_{3}$ of strength $-1$. Given the build order, we are guaranteed $f_{i}^{out}$ and that $t_{i}^{out}$ can not build.

• 2.

If $f_{i}^{in}$ enters a NOT gadget, it results in $t_{i}^{out}$ and not $f_{i}^{out}$. Figure 6(c) shows the gadget in this case$-$ with false input $f_{i}^{in}$ and output $t_{i}^{out}$. The false output can not attach due to the negative glue $n_{2}$. The tile to the west of $x$ may attach, but due to glue $n_{3}$, no other tile can attach. Given the build order, we are guaranteed $t_{i}^{out}$ and that $f_{i}^{out}$ can not build.

• 3.

The $t_{i}^{in}$ wire will be backfilled up to tile $x$ if and only if $f_{i}^{in}$ enters a NOT gadget and $t_{i}^{out}$ leaves. Figure 6(d) shows the desired result. Glues $h_{5},h_{6}$ allow the true portion and wire to backfill. Glue $h_{1}$ is needed to counteract the $n_{1}$ glue when backfilling that tile. Then the logic diode ensures $f_{i}^{in}$ is present to backfill the wire.

• 4.

The $f_{i}^{in}$ wire will be backfilled up to tile $x$ if and only if $t_{i}^{in}$ enters a NOT gadget and $f_{i}^{out}$ leaves. Figure 6(b) shows the desired result. Glues $h_{3},h_{4}$ allow the true portion and wire to backfill. Glue $h_{2}$ is needed to fill in the tile with $n_{2}$. Then the logic diode ensures $t_{i}^{in}$ is present to backfill the wire.

• 5.

If the gadget resulted in $f_{i}^{out}$, a future gadget can backfill $t_{i}^{out}$ and the gadget will be complete. If the gadget is in the configuration of Figure 6(b), the true wire can directly backfill until the tile directly above tile $x$. The glue $n_{1}$ would prevent this tile from placing except $x$ will be there and the tile can cooperatively attach using the north glue of $x$ and the south glue of the backfilling wire.

• 6.

If the gadget resulted in $t_{i}^{out}$, a future gadget can backfill $f_{i}^{out}$ and the gadget will be complete. If the gadget is in the configuration of Figure 6(d), the false wire can directly backfill until the tile directly east of tile $x$. The glue $n_{2}$ would prevent this tile from placing except $x$ is there and the tile can cooperatively attach using the east glue of $x$ and the west glue of the backfilling wire.

3.5 Covert NAND Gadget

The basic idea for the NAND gadget is to compare if both inputs are true, but because of the planarity constraints, we need to “flip” one of the inputs using a covert NOT before comparing. Since a NAND is false only when both inputs are true, this is the only path that should result in a false output. The basic idea for the gadget is shown in Figure 7(a) with a representative block for the NOT gadget already discussed. The second NOT block is the modified NOT gadget (H-NOT) from Figure 5(c). Both false inputs are routed to the true output. One must go through another NOT in order to flip to the top output position, while the other false line skips this NOT and ties directly to the true output. Once we flip the top input, we can use cooperative binding to compare the two true inputs, and only if both are true do we send it as true into the second NOT block (so the gadget outputs false). All other input combinations output true.

We will show why NOT and H-NOT are both necessary. Looking at Figure 7(b), the negative glue $n_{H}$ is necessary in H-NOT to ensure that $t_{i}^{out}$, which skips the second NOT gadget, does not set the output $t_{ij}^{out}$, and then also set $f_{ij}^{out}$ based on the assembly order. Essentially, this protects from incorrect backfilling and setting both outputs. However, the $n_{H}$ glue should not exist in the standard NOT gadget, or it may backfill and could cause a tile to break off depending on build order. Given we are using the growth-only aTAM, this would not be allowed. It is possible to create a single NOT that incorporates these properties, but we prefer to avoid the added complexity.

Finally, the logic diodes on the inputs (Figure 4(b)) ensure that if we only have one input, the gadget does not backfill down the other input wire. Even if the gadget has already been set, that input will wait until either the true or false wire comes before backfilling the wire.

Given the complexity of the NAND gadget, there are more issues related to its function that must be considered compared to the previous gadgets. The properties that it must have are as follows.

• 1.

If wires $t_{i}^{in}$ and $t_{j}^{in}$ are set, then the wire $f_{ij}^{out}$ should leave the gadget. Wire $t_{i}^{in}$ exits the first NOT gadget as $f_{i}^{out}$. This wire, $f_{i}^{out}$, and $t_{j}^{in}$ both stop and expose glues $a_{2}$ and $a_{3}$, respectively. Both are strength 1 glues, and thus the tile with glues $a_{2}$ and $a_{3}$ can only attach if both the glues are exposed. Thus, only if wires $t_{i}^{in}$ and $t_{j}^{in}$ are set, will wire $t_{ij}^{in}$ ever enter the H-NOT gadget, which results in the wire $f_{ij}^{out}$ as the gadget output.

• 2.

Given $f_{i}^{in}$ or $f_{j}^{in}$, the wire $t_{ij}^{out}$ leaves the gadget. If wire $f_{i}^{in}=t_{i}^{out}$ is set, this is tied directly to the output wire $t_{ij}^{out}$. If the wire $f_{j}^{in}$ is set, it comes in as the false input of the second H-NOT gadget, which means it leaves as $t_{ij}^{out}$ by the validity of the NOT gadget.

• 3.

The wires $t_{i}^{in}$ and $f_{j}^{in}$ ($f_{i}^{in}$ and $t_{j}^{in}$ input) are backfilled if $t_{ij}^{out}$ left the gadget. If $t_{ij}^{out}$ left the gadget, then it directly can backfill both the $t_{i}^{out}$ wire of the NOT gadget and the $f_{j}^{in}$ wire if not already filled. Thus, $f_{j}^{in}$ is filled. Since the input line $t_{i}^{out}$ of the NOT is filled, it backfills $t_{i}^{in}$ as shown for the NOT gadget. Both wires are then backfilled through cooperative attachment with the presence of the other input in the logic diode.

• 4.

The wires $f_{i}^{in}$ and $t_{j}^{in}$ ($t_{i}^{in}$ and $f_{j}^{in}$ input) are backfilled if $t_{ij}^{out}$ left the gadget. If $t_{ij}^{out}$ left the gadget, then it directly can backfill both the $t_{i}^{out}$ wire of the NOT gadget and the $f_{j}^{in}$ wire if not already filled. The true output of the H-NOT gadget backfills and glues $a_{3},a_{4}$ allow the cooperative attachment that backfills $t_{j}^{in}$. The NOT gadget with the true input would backfill $f_{i}^{in}$. Both wires are then backfilled through cooperative attachment with the presence of the other input in the logic diode.

• 5.

The wires $t_{i}^{in}$ and $t_{j}^{in}$ ($f_{i}^{in}$ and $f_{j}^{in}$ input) are backfilled if $t_{ij}^{out}$ left the gadget. If $t_{ij}^{out}$ left the gadget, then it directly can backfill both the $t_{i}^{out}$ wire of the NOT gadget and the $f_{j}^{in}$ wire if not already filled. The NOT gadget with $f_{i}^{in}$ input will backfill $t_{i}^{in}$. The true output of the H-NOT gadget backfills and glues $a_{3},a_{4}$ allow the cooperative attachment that backfills $t_{j}^{in}$. Both wires are then backfilled through cooperative attachment with the presence of the other input in the logic diode.

• 6.

The wires $f_{i}^{in}$ and $f_{j}^{in}$ ($t_{i}^{in}$ and $t_{j}^{in}$ input) are backfilled if $f_{ij}^{out}$ left the gadget. The NOT gadget with the true input would backfill $f_{i}^{in}$. The H-NOT gadget will backfill the false input line, which is $f_{j}^{in}$. Both wires are then backfilled through cooperative attachment with the presence of the other input in the logic diode.

• 7.

The wire $f_{i}^{out}$ is always placed. The glues $a_{1},a_{2}$ ensure that if all previous properties hold, the false output wire ($f_{i}^{out}$) is also filled. Stepping through properties 3-6, it is possible for the gadget to backfill the input wires correctly without always placing these tiles.

• 8.

The growth-only constraint is not violated with the negative glues. This can only happen given a stable assembly where a tile attaches with a negative glue that destabilizes part of the assembly. The additional negative glue $n_{H}$ could do this if the green tile is placed after the blue tile, however, the build path is intentional to ensure this can not happen. If the wire $f_{ij}^{out}$ were placed and $t_{ij}^{out}$ is backfilled, the tile with $n_{H}$ would be the last tile that could attach and the assembly would never be unstable.

• 9.

The gadget does not behave incorrectly with only one input. The logic diode guarantees the backfilling never goes beyond the gadget. If one input is false, the NAND can send the $t_{ij}^{out}$ wire and backfill the NAND gadget without having yet receieved the second input. When the second wire does arrives, that wire is backfilled. With one true input, the gadget will just be waiting at the tile needing both $a_{2}$ or $a_{3}$. $t_{i}^{in}$ will also backfill $f_{i}^{in}$ even with only that input. Given $t_{j}^{in}$, the false line is not backfilled until both inputs are there.

3.6 Covert FANOUT Gadget

The FANOUT gadget needs to duplicate the geometric wire, and needs to backfill when at least one of the outgoing wires has backfilled. Figure 8(a) shows the FANOUT gadget. Similar to the NOT, there is a shared set of tiles placed by both the true and the false path. Figures 8(c) and 8(c) show the true and false paths without any backfilling, respectively. For a FANOUT, we add a Backfill Stop gadget to both of its outputs in order to ensure they are backfilled. This is not necessary, but it ensures that the gadget always backfills even when one of the outputs is part of the output of the computation.

The FANOUT has the following necessary properties.

• 1.

With input $t_{i}^{in}$, the gadget outputs wires $t_{i}^{out_{1}}$ and $t_{i}^{out_{2}}$, and does not output $f_{i}^{out_{1}}$ and $f_{i}^{out_{2}}$. Figure 8(c) shows the true fanout without the backfilling. Due to $n_{1}$ and $n_{2}$, the false outputs can not assemble. Both settings share the same middle four tiles, but with placement order $n_{1}$ is placed first and then cooperative glues are used to place the first tile of the four (with glues $g_{3},g_{4}$).

• 2.

With input $f_{i}^{in}$, the gadget outputs wires $f_{i}^{out_{1}}$ and $f_{i}^{out_{2}}$, and does not output $t_{i}^{out_{1}}$ and $t_{i}^{out_{2}}$. Figure 8(c) shows the false fanout without the backfilling. Due to $n_{1}$ and $n_{2}$, the true outputs can not assemble. With placement order $n_{2}$ is placed first and then cooperative glues are used to place the first of the four middle tiles (with glues $h_{3},h_{4}$).

• 3.

With input wire $t_{i}^{in}$, wire $f_{i}^{in}$ only backfills once $f_{i}^{out_{1}}$ or $f_{i}^{out_{2}}$ have backfilled. Both wires backfill independently, and only $f_{i}^{out_{2}}$ can actually backfill the $f_{i}^{in}$ wire. However, much like the logic diodes at the input of the gadget, we require a backfill stop gadget on both of the outputs of the FANOUT. This means that both $f_{i}^{out_{1}}$ and $f_{i}^{out_{2}}$ are backfilled.

• 4.

With input wire $f_{i}^{in}$, wire $t_{i}^{in}$ only backfills once $t_{i}^{out_{1}}$ or $t_{i}^{out_{2}}$ have backfilled. Both wires backfill independently, and only $t_{i}^{out_{1}}$ can actually backfill the $t_{i}^{in}$ wire. However, much like the logic diodes at the input of the gadget, we require a backfill stop gadget on both of the outputs of the FANOUT. This means that both $t_{i}^{out_{1}}$ and $t_{i}^{out_{2}}$ are backfilled.

4 Covert Computation and Unique Assembly Verification

In this section we establish our main results related to covert computation in self-assembly systems. We first utilize our covert circuitry to show that any function is covertly computable (Thm. 1). We then apply covert circuitry to show that the open problem of Unique Assembly Verification within the growth-only negative glue aTAM is coNP-complete (Thm. 2).

Theorem 1**.**

For any function $f$ computed by a boolean circuit, there exists a tile assembly computer (TAC) that covertly computes $f$.

Proof.

The proof of this theorem consists of a direct simulation of boolean circuits by way of a series of covert gadget implementations for various logic gates and how to connect them. NAND Boolean gates are functionally complete when combined with a FANOUT [27], and can implement any Boolean circuit. These are easily transformed into Circuit SAT instances to compute any function that is in the class NP [15], which fits within our definition of computable functions by a TAC. Thus, the proof follows from the gadgets and machinery given in Section 3 that implement the variables and gates for Circuit SAT. $\square$ ∎

We now prove that Unique Assembly Verification (UAV) in a growth-only negative glue aTAM system is coNP-complete by utilizing our covert gadgets. Without the growth-only constraint, UAV in the negative glue atam is undecidable as a Turing machine simulation could use negative interactions to break down produced assemblies into a final unique terminal assembly exactly when the Turing machine halts [11]. With no negative glues however, the problem is in P [1]. We prove that with the ability to temporarily block, the problem becomes coNP-complete. This result is achieved with a reduction from Circuit SAT. Unique Assembly Verification in our model is formally defined as follows:

Definition 1** (Unique Assembly Verification (growth only)).**

Given a negative-glue aTAM tile-system $\Gamma=(T,S,\tau)$ with the promise that it is a growth-only system, and an assembly $A$. Does $\Gamma$ uniquely assemble $A$?

A reduction from Circuit SAT [15] generally requires a functionally universal set of gates and variable, wire, fanout, and crossover gadgets. Both NAND and NOR are functionally complete gates, so given either, all gates can be made. A crossover gadget is redundant since it can be made with XOR gates and XOR gates can be made with NAND gates [26]. Figure 9 shows this derivation. Finally, Circuit SAT requires a DAG, and thus there are no cycles, and so the gadgets can be topologically sorted so that there are no crossovers that cause a loop (the output of a gadget can not crossover one of its input lines). Thus, a reduction from Planar Circuit SAT is equivalent to a reduction from Circuit SAT.

Definition 2** (Planar Circuit SAT).**

Given a planar directed acyclic graph (DAG) $G=(V,E)$ with $n$ boolean inputs, one output, and every $v\in V$ is either a NAND (or NOR) gate ($deg^{-}(v)=2$, $deg^{+}(v)=1$) or a fanout ($deg^{-}(v)=1$, $deg^{+}(v)=2$), the source vertices ($v_{i}\in V$ s.t. $deg^{-}(v_{i})=0$ and $1\leq i\leq n$) are the variables, and the sink vertex ($s\in V$ s.t. $deg^{+}(v_{i})=0$) is the “output” of the boolean circuit. Does there exist a setting of the inputs such that the output to the circuit is 1?

Theorem 2**.**

Unique Assembly Verification in the aTAM with repulsive forces in a growth only system is coNP-complete.

Proof.

We first observe that Unique Assembly Verification with repulsive forces is in coNP as any failure to uniquely assemble a target assembly $A$ comes in the form of a polynomially sized assembly that is inconsistent with $A$. The producibility of this assembly can be verified in polynomial time, and thus serves as a certificate for “no” instances to the UAV problem.

We now show coNP-hardness by a reduction from Planar Circuit SAT. Assume we are given an arbitrary instance of planar Circuit SAT $C$ with inputs $i_{1},\dots,i_{n}$ where $i\in\{0,1\}$, i.e., a boolean circuit. By our definition we assume there are only NAND gates, fanouts, input variables and an ouput variable in the planar DAG.

For our reduction, we build a tileset $T$ by adding tiles corresponding to the covert gadgets and connections described in Section 3. Replace each NAND gate with a unique set of tiles implementing a NAND gadget, and each FANOUT gate with a unique set of tiles implementing a FANOUT gadget. For each edge, a unique sequence of tiles is added to $T$ that connects the two gadgets representing the two gates the edge connected.

This yields a tile assembly computer (TAC), $\Im=(T,I,O,\tau)$, for covertly computing the circuit $C$. The key modification to show coNP-hardness is the utilization of a seed that non-deterministically grows any one of the possible $n$-bit input seeds for this TAC, and then evaluates the circuit. If the circuit is not-satisfiable, then the final computation will be false regardless of the guessed input, and therefore will yield the unique “no” assembly of the TAC based on the fact that the circuit is computed covertly. On the other hand, if there exists some satisfying $n$-bit input, there will be at least one final assembly that differs from the “no” assembly. Thus, the “no” assembly is uniquely produced if and only if the circuit $C$ is not satisfiable, thereby showing coNP-hardness.

Non-deterministic input selection. To non-deterministically form the possible input bits, we include the tile types and seed tile described in Figure 3(b). The seed grows a length $O(n)$ line with each bit being encoded by a pair of adjacent locations which expose a glue on the north edge. For each pair of positions, the presence of the left tile denotes a “1” for the respective bit, and the placement of the right tile denotes a “0”. The “1” and “0” tiles share a negative strength $1$ glue, making their mutual placement impossible until the covert gadgets have passed on the computed signal and backfilled. $\square$ ∎

Given that UAV is coNP-complete with negative glues by way of covert circuitry, yet UAV is in $P$ without negative glues [1], it is reasonable to conjecture that the use of negative interactions is needed to perform covert computation.

Conjecture 1**.**

For some function $f$ computed by a boolean circuit, there does not exist a polynomially-sized tile assembly computer (TAC) that covertly computes $f$ in the aTAM without negative glues.

5 Further Motivation

Here, we give a few more motivating examples and some simplified gadgets. There is a lot of future work in this vein of research that is extremely relevant to modern society. We first cover the covert AND and OR gadgets.

5.1 Simplified Gadgets

Even though NAND gates alone are functionally complete, for some gates the circuit is larger than desired. Here, we give compact direct versions of some other useful gadgets and gates. This does not affect the complexity, but does help build a more efficient covert computation toolkit.

Covert AND Gadget. The covert AND gadget is nearly identical to the NAND gadget. The only real difference is which two inputs the second NOT takes in. Also, similar to the H-NOT needed for the NAND, we create a V-NOT, which is a NOT with one additional vertically aligned negative glue. Figure 10(a) shows the AND gadget with the blocks in place of NOTs for clarity, and Figure 10(b) shows the full gadget.

Covert OR Gadget. The covert OR gadget still uses a NOT to flip one of the inputs, but does several checks on the second flip to the point of drastically differing from a NOT. This is similar to needing H-NOT and V-NOT in previous gadgets to handle specific issues related to the boolean function, but more changes are required. Figure 11(a) shows the OR gadget with the blocks in place of NOTs for clarity, and Figure 11(b) shows the full gadget.

5.2 Encryption and Cryptography

Several encryption methods are based off problems that we believe to be “hard” computationally. One of the most common is factoring the product of large prime numbers, which is the basis for several encryption schemes. Although factoring may be difficult, the function to generate the number is simple multiplication, which can be accomplished with simple circuits. Figure 12(d) shows a simple 6-gate circuit implementing a 2-bit number multiplier resulting in a 4-bit output number. An $n$-bit multiplier scales linearly (in the number of bits) with additional AND gates and full and half adders.

Implementing the multiplier with covert gates is not difficult, but the resulting assembly is large due to the inefficient crossover gadget used. Instead, we demonstrate a simple half-adder. The schematic for a half-adder is in Figure 12(c). A covert half-adder as a TAC is shown in Figure 13(b). The XOR has been replaced by the 4 NAND gates as shown in Figure 9(e). Further, 3 FANOUTs were needed, an AND gadget as shown above in Section 5.1, and 2 NOT gadgets were used to flip the input for the gadgets. Figure 13(a) shows the four possible input seeds to build the assembly.

6 Conclusions and Future Work

We have introduced the concept of covert computation in self-assembly and provided a general scheme to implement any boolean circuit under this restriction. Beyond potential applications to biomedical privacy, cryptography, and intellectual property, our techniques and framework promise to impact self-assembly theory itself. As a first example we have applied our techniques to the fundamental problem of Unique Assembly Verification in the negative glue aTAM, and shown it to be coNP-complete with growth-only systems, essentially as a corollary of our covert computation theory.

A number of future directions stem from our work. Having established the general computation power of covert computation, a natural next step is the consideration of efficiency for computing classes of functions. The time complexity of self-assembly computation has been studied [2, 18] and shown to allow for a substantial amount of parallelism. Can similar results be achieved under the covert constraint? What general connections exists between the time complexity for unrestricted self-assembly computation versus that of covert computation? Other natural metrics include minimizing the number of distinct tile types, along with the space taken up by the final assembly of the computation.

Another future direction is to investigate what model features are required for covert computation. In this paper, we conjectured that there does not exists a tile assembly computer that performs covert computation in the aTAM without negative glues. This conjecture is made with the assumption that no other model definitions change. If other definition relaxations are made to the model, such as allowing assemblies which are equal up to translation to be considered the same assembly, might covert computation be possible without negative glues?