Investigation of the Power Consumption of the PETsys TOFPET2 ASIC

TL;DR

This paper evaluates the power consumption of the PETsys TOFPET2 ASIC, demonstrating its suitability for PET/MR systems due to low power use and high performance, with an analytical model for configuration optimization.

Contribution

It provides the first detailed analysis of the TOFPET2 ASIC's power consumption and presents an analytical model to optimize its configuration for PET/MR applications.

Findings

Power consumption ranges from 3.6 to 7.2 mW/channel.

Configured input impedance and noise affect resolution and trigger levels.

TOFPET2 ASIC offers competitive performance with low power use.

Abstract

In state-of-the-art positron emission (PET) tomography systems, application-specific integrated circuits (ASICs)are commonly used to precisely digitize the signals of analog silicon photo-multipliers (SiPMs). However, when operating PET electronics in a magnetic resonance (MR) system, one faces the challenge of mutual interference of these imaging techniques. To prevent signal deterioration along long analog signal lines, PET electronics with a low power consumption digitizing the signals close to the SiPMs are preferred. In this study, we evaluate the power consumption of the TOFPET2 ASIC. Its power consumption ranges from 3.6 to 7.2 mW/channel as a function of the input stage impedance and discriminator noise settings. We present an analytical model allowing to compute the power consumption of a given ASIC configuration. The configured input stage impedance and discriminator noise have an impact on the coincidence resolution time, energy resolution, and photon trigger level. Since the TOFPET2 ASIC delivers state-of-the-art performance with a power consumption similar or even lower than other ASICs typically used for PET applications, it is a favorable candidate to digitize the signals of SiPMs in future simultaneous PET/MR systems.

Tables

Table 1. Table I: Power consumption of the TOFPET2 ASIC measured at minimum, default, and maximum setting. The parameters 𝖿𝖾 ​ _ ​ 𝗂𝖻𝟣 𝖿𝖾 _ 𝗂𝖻𝟣 \mathsf{fe\_ib1} , 𝖿𝖾 ​ _ ​ 𝗂𝖻𝟤 𝖿𝖾 _ 𝗂𝖻𝟤 \mathsf{fe\_ib2} , and 𝖽𝗂𝗌𝖼 ​ _ ​ 𝗌𝖿 ​ _ ​ 𝖻𝗂𝖺𝗌 𝖽𝗂𝗌𝖼 _ 𝗌𝖿 _ 𝖻𝗂𝖺𝗌 \mathsf{disc\_sf\_bias} are software configuration variables.

	$\mathrm{𝖿𝖾}\_\mathrm{𝗂𝖻𝟣}$	$\mathrm{𝖿𝖾}\_\mathrm{𝗂𝖻𝟤}$	$\mathrm{𝖽𝗂𝗌𝖼}\_\mathrm{𝗌𝖿}\_\mathrm{𝖻𝗂𝖺𝗌}$	$P$ / mW/channel
minimum	60	30	32	3.6
default	59	0	0	6.4
maximum	0	0	0	7.2

Table 2. Table II: Parameters of the analytical model to compute the TOFPET2 power consumption from software configuration parameters. Parameters are computed mean values of the fit parameters determined using a least-squares fit routine.

parameter	value /$\mathrm{mW}/\mathrm{channel}$
\acf0	$\left(-9.96\pm 0.03\right)\cdot {10}^{-3}$
\aca0	$\left(-2.53\pm 0.02\right)\cdot {10}^{-3}$
\aca1	$\left(-0.60\pm 0.01\right)\cdot {10}^{-3}$
\aca2	$\left(23.17\pm 1.12\right)\cdot {10}^{-3}$
\acb0	$\left(-45.41\pm 0.17\right)\cdot {10}^{-3}$
\acb1	$\left(2.74\pm 0.02\right)\cdot {10}^{-3}$
\acb2	$\left(6.70\pm 0.86\right)\cdot {10}^{-3}$
$P_0^{\ast }$	7.07
∗Value was determined experimentally.

Table 3. Table III: Comparison of power consumption and single-channel performance between different ASIC models.

ASIC	Timestamp Digitization	Charge Measurement	Power Consumption	CRT / ps	Crystal Height	Ref.
			/ mW/channel		/ mm
FlexToT	external	tot output	11	123	5	[52, 53]
HRFlexToT	external	tot comparator	3.5	180	20	[54, 55]
NINO	external	tot method	27	93	5	[52, 56]
STiC3	TDC on ASIC	tot method (TDC on ASIC)	25	240	15	[23]
PETA4	TDC on ASIC	qdc method (ADC on ASIC)	40	460	25	[20]
Petiroc	external	tot output	3.5 (w/o ASIC buffers)	n.a.	n.a.	[19, 28]
Triroc	TDC on ASIC	qdc method (ADC on ASIC)	10	432.7	10	[22]
TOFPET1	TDC on ASIC	tot method (TDC on ASIC)	8 - 11	290.7	15	[34, 57]
TOFPET2	TDC on ASIC	qdc method (ADC on ASIC)	3.6 - 7.2 (+ 1.2)∗	210	5	[49]
TOFPET2	TDC on ASIC	qdc method (ADC on ASIC)	5 - 8	202	5	[44, 58]
∗Values were determined experimentally.

Equations

$$\bar{P}=U_{DD12}\cdot {\bar{I}}_{DD12}=U_{DD12}\cdot \frac{\Delta \bar{U}}{R}$$

$$E=c\cdot s\cdot \log \left(\frac{1}{1-\frac{e}{s}}\right)$$

$$U_{\mathsf{cor},\mathsf{rel}}=\frac{U_{\mathsf{bias},\mathsf{set}}-U_{\mathsf{off}}-{\bar{U}}_{\mathsf{BD}}}{{\bar{U}}_{\mathsf{BD}}},$$

$$P_{\mathsf{ch}}=P_0+d{P}_{fe\_ib1}+d{P}_{fe\_ib2}+d{P}_{disc\_sf\_bias}$$

$$d{P}_{disc\_sf\_bias}=\{\begin{array}{ll}{f}_0\cdot disc\_sf\_bias,& \\ 0\le disc\_sf\_bias\le 32& \end{array}$$

$$d{P}_{fe\_ib1}=\{\begin{array}{ll}{a}_1\cdot fe\_ib1,& 0\le fe\_ib1\le 40\\ & \\ a_2\cdot {fe\_ib1}^2& \\ +a_3\cdot fe\_ib1,& 41\le fe\_ib1\le 60\end{array}$$

$$d{P}_{fe\_ib2}=\{\begin{array}{ll}{b}_0\cdot fe\_ib2,& 0\le fe\_ib2\le 20\\ & \\ b_1\cdot {fe\_ib2}^2& \\ +b_2\cdot fe\_ib2,& 21\le fe\_ib2\le 30\end{array}$$

Full text

I Introduction

In positron emission tomography (PET), radioactive tracer molecules are injected into the patient’s body. The tracer molecules undergo a $\beta^{+}$-decay resulting in the emission of a positron which annihilates with an electron in the surrounding tissue. Two $\gamma$-photons released back-to-back by the electron-positron annihilation with an energy of $511\text{\,}\mathrm{keV}$ each are detected by a ring-shaped array of $\gamma$-detectors surrounding the patient [1, 2, 3]. Based on these so-called coincidence events, PET is used as a functional imaging technique in oncology, neurology and cardiology [4, 5, 6].

Common state-of-the-art PET systems employ scintillators fabricated of lutetium-(yttrium-)oxyorthosilicate doped with cerium (L(Y)SO) converting incident $\gamma$-photons into optical photons and analog silicon-photomultipliers (SiPMs) as photo-detectors, which have come to replace previously used avalanche photo-diodes (APDs) during the past years [7]. An SiPM consists of several thousand single-photon avalanche diodes (SPADs) which are connected in parallel. The term SPAD refers to avalanche photo-diodes (APDs), which are operated in Geiger mode. The SPADs break down and generate an analog pulse when hit by an optical photon. The signal sum is a measure for the number of detected photons. The timestamp of the detected $\gamma$-interaction can be determined from the first optical photons detected by the SiPM. Passive quenching of the self-sustaining avalanche resulting from a diode breakdown and thus, resetting the diode is achieved by a serial high-ohmic resistance per individual SPAD. Using time-of-flight (TOF) information, PET systems are capable of resolving the difference in arrival times of the two $\gamma$-photons of a coincidence event down to the order of few hundred picoseconds. This allows to localize the annihilation event more precisely, which can be exploited during image reconstruction leading to a better signal-to-noise ratio (SNR) of the image of the activity distribution [8, 9, 2, 1]. State-of-the-art clinical systems reach coincidence resolution times (CRTs) down to $214\text{\,}\mathrm{ps}$ – a benchmark set by the Siemens Biograph Vision PET/CT system [10]. In benchtop experiments, much lower CRTs down to $58\text{\,}\mathrm{ps}$ are possible [11, 12].

For SiPM readout in PET applications, the precise digitization of event timestamps and energies is typically achieved by employing application-specific integrated circuits (ASICs). These ASICs typically support 8 to 64 data channels [13, 14, 15, 16, 17, 18, 19, 20, 21, 22]. The time binning of the employed time-to-digital converters (TDC) can range from $2050\text{\,}\mathrm{ps}$ [21, 23, 20, 24]. The energy of the signal can either be measured by a time-over-threshold method (tot-mode) [14, 25, 26, 27] or via signal integration (qdc-mode), e.g., as applied for the Weeroc, PETA and TOFPET ASIC series [21, 22, 28, 29, 16, 30, 20, 31, 32, 33, 13, 34, 35, 36]. The measurement can be linear for integrating charges up to $20003000\text{\,}\mathrm{p.e.}$ (photo-electrons) [22, 36, 19].

When integrating TOF-PET and magnetic resonance imaging (MRI) in one hybrid system, one faces the need of a compact infrastructure designed for the only restricted space inside the MR bore as well as problems of dissipation and mutual interference. These can result in performance degradation for both imaging modalities and, thus, need to be evaluated [37, 38, 39]. In addition, one has to take into account the power supply that is required by the high-performance PET electronics. Connecting the PET electronics to the SiPMs via long cables from outside to prevent space problems inside the MR system potentially leads to a performance degradation due to a loss of the SiPM signal quality, e.g., as specified for the use of the TOFPET2 ASIC [40]. The signal quality is deterioated by the increased inductance and impedance on the signal line. The long analog signal lines would additionally call for sophisticated shielding to avoid a distortion of the transmitted signals by the dynamic magnetic fields of the MR system. An early digitization close to the SiPM should therefore be considered.

To this end, the power for the PET electronics has to be provided via circuitry inside the MR bore. The MR-environment puts a lot of constraints on the selection of the power supply electronics, complicating the use of switched mode power supplies (SMPS). Hence, linear voltage regulators are often used to provide the final supply voltage for the PET electronics, whose design as well as the required infrastructure benefits from low-power PET electronics [41, 42]. For those reasons, PET electronics with a low power consumption are favored for system integration to overcome the aforementioned effects.

This study aims to characterize the power consumption of the TOFPET2 ASIC, which was released by PETsys Electronics S.A. in 2017 [43]. In addition, the possible impact of the power consumption configuration on the ASIC performance is evaluated to further assess the system applicability of the TOFPET2 ASIC.

II Materials

II-A Setup

We used the TOFPET2 ASIC evaluation kit provided by PETsys Electronics S.A. (see Fig. 1) [35, 44, 45, 46]. The evaluation kit allows the user to test the TOFPET2 ASIC under benchtop conditions with different SiPM types. The SiPMs can be connected to the ASIC via two SAMTEC connectors on the ASIC test boards shipped with the kit. Apart from these test boards, the kit includes a front end board (FEB/D) holding the power supply and external clock for the ASIC test boards as well as a field programmable gate array (FPGA) and a 1-Gbit-Ethernet link for data transmission. In addition, a high-voltage digital-to-analog converter (HV-DAC) mezzanine board is employed to provide the bias voltage for the SiPMs used. The two ASIC test boards can be connected to the FEB/D board via two flexible cables and are mounted on a bread board for coincidence experiments (see Fig. 1). The whole setup is enclosed by a light-impermeable top cover featuring a fan. We added a temperature sensor connected to a controller allowing to adjust the ambient temperature of the setup. The setup including FEB/D board is placed into a larger climate chamber, which is likewise thermally controlled.

II-B TOFPET2 ASIC

The TOFPET2 ASIC (version 2b) features 64 individual channels, two TDCs with a time binning of $30\text{\,}\mathrm{ps}$, and a clock cycle of $200\text{\,}\mathrm{MHz}$ [35]. The user can choose a tot- or qdc-mode to measure the signal energy. The analog-to-digital converters (ADCs) used for the latter one are linear for integrating charges up to $1500\text{\,}\mathrm{pC}$ ($2500\text{\,}\mathrm{p.e.}$) [47]. During acquisition, each channel is multi-buffered by four analog buffers. The maximum event rate per ASIC channel is $600\text{\,}\mathrm{kcps}$ [48]. Each channel features an individual trigger circuit designed to reject dark counts by a three-threshold event validation. Two discriminators $\mathsf{D\_T1}$ and $\mathsf{D\_T2}$ in the timing branch of the circuit are configured to trigger on different voltage thresholds, whereby the lower trigger of discriminator $\mathsf{D\_T1}$ is fed into an $\mathsf{AND}$ gate and validated by the higher trigger of discriminator $\mathsf{D\_T2}$. A third discriminator $\mathsf{D\_E}$ with an even higher threshold is employed in the energy branch for further noise rejection. Using the default trigger setting, an event is considered valid, if it triggers all three discriminators. The voltage threshold of each discriminator can be adjusted via a dimensionless parameter $\mathsf{vth\_t1}$, $\mathsf{vth\_t2}$ or $\mathsf{vth\_e}$, respectively. These parameters operate on different scales (approx. $2.5\text{\,}\mathrm{mV}$, $15\text{\,}\mathrm{mV}$, and $20\text{\,}\mathrm{mV}$ per DAC step [49]) and adjust the voltage threshold over a channel-specific baseline determined in the calibration routine. If an incident event only triggers $\mathsf{D\_T1}$, it is rejected. On this first validation level, no dead time is introduced by the event rejection. If an incident event also triggers $\mathsf{D\_T2}$, the event timestamp is generated by this second trigger. Hereafter, the event is validated or rejected by the third trigger.

It is possible that small pulses occurring just before coincidence events trigger $\mathsf{D\_T1}$ and are validated by the real event triggering $\mathsf{D\_T2}$ right after. This causes the event timestamp to be generated by the output of $\mathsf{D\_T2}$ instead of the delayed output of $\mathsf{D\_T1}$ ($\mathsf{D\_T1^{\prime}}$). Subtracting two timestamps matched as a coincidence, where one was regularly assigned by $\mathsf{D\_T1^{\prime}}$ and one was falsely generated by $\mathsf{D\_T2}$, results in a coincidence time difference modulated by the trigger delay period. In the time difference spectra of matched coincidence events, these time differences are visible as satellite peaks shifted from the main peak by the trigger delay period (see Fig. 2). A detailed description of the operation of the trigger circuit and the appearance of satellite peaks can be found in [49].

Three software configuration parameters influence the input stage impedance $R_{\mathsf{IN}}$ and the discriminator noise of the TOFPET2 ASIC channel circuit, which both can be used to adjust the power consumption of the TOFPET2 ASIC. All parameters operate on a dimensionless scale. The parameters $\mathsf{fe\_ib1}$ and $\mathsf{fe\_ib2}$ affect the load on the signal line. By changing $\mathsf{fe\_ib1}$, the input impedance can be adjusted. The impedance is exponentially increased from $1132\text{\,}\mathrm{\SIUnitSymbolOhm}$ when $\mathsf{fe\_ib1}$ is changed from 0 to 60, which reduces a current $\mathsf{I_{B1}}$ in the preamplifier circuit [35]. Considering a parasitic capacitance on this line, a higher input stage impedance leads to a slower signal. The discriminator noise $\mathsf{V_{noise\_T}}$ and the discriminator noise slew rate, respectively, can be adjusted by changing the parameters $\mathsf{fe\_ib2}$ and $\mathsf{disc\_sf\_bias}$. The parameter $\mathsf{fe\_ib2}$ modifies a current $\mathsf{I_{B2}}$ in the preamplifier circuit, which changes the signal amplification. Details on the preamplifier circuit, which itself consumes $2.5\text{\,}\mathrm{mW/channel}$, are given in [47]. The parameter $\mathsf{disc\_sf\_bias}$ affects the biasing of signal buffers between two blocks, in which the discriminators are divided. Reducing the buffer biasing by choosing a smaller value for $\mathsf{disc\_sf\_bias}$, we expect a slower internal copy of the signal. We use the nomenclature from the PETsys documentation [35]. No numerical values are given regarding the impact of $\mathsf{fe\_ib2}$ and $\mathsf{disc\_sf\_bias}$ on physical parameters [35].

II-C $\gamma$-Detectors

In this study, three configurations of SiPMs and scintillators were used with the setup. For single-channel experiments, we employed two FBK (NUV-HD) SiPMs each coupled to a $2.62\text{\times}2.62\text{\times}3\text{\,}\mathrm{mm}$ LYSO scintillation crystal using Cargille Meltmount™ ($\mathsf{n_{D}}=1.539$). To connect these to the ASIC test boards, two small adapter boards provided by PETsys were used. A 22Na point source ($0.5\text{\,}\mathrm{mm}$ active diameter) with an activity of approx. $7\text{\,}\mathrm{MBq}$ was placed in the center of the setup. For multi-channel experiments, we employed two 8 $\times$ 8 KETEK PA3325-WB-0808 SiPM arrays or two 8 $\times$ 8 Hamamatsu S14161-3050-HS-08, each one-to-one coupled to a 12-mm-high scintillator array, featuring BaSO4 powder mixed with epoxy as the inter-crystal layer. An individual crystal has the dimensions $3\text{\times}3\text{\times}12\text{\,}\mathrm{mm}$. For optical coupling, Sylgard® 527, a two-component dielectric gel fabricated by Dow Corning, was used. A geometry of five 22Na NEMA cubes ($0.25\text{\,}\mathrm{mm}$ active diameter, $10\text{\,}\mathrm{mm}$ edge length, suggested to be used for resolution testing according to the NEMA NU4-2008 standards [50]) with a total activity of approx. $3\text{\,}\mathrm{MBq}$ was placed in the center of the setup. All single- and multi-channel configurations were wrapped in teflon tape to prevent light loss.

III Methods

In this work, the power consumption of the TOFPET2 ASIC was quantified, including a study of the range of possible configurations. The power consumption of the TOFPET2 ASIC is a function of the input stage impedance, the discriminator noise, and its slew rate. Adjustments of the configuration parameters are expected to affect the ASIC performance. This performance impact was also evaluated. The available configuration parameters do not allow to adjust the input capacitance, which influences the ASIC power consumption as well, but cannot be configured [35].

III-A Experiments

The ASIC requires a power supply of $1.2\text{\,}\mathrm{V}$ powering the ASIC operation and a power supply of $2.5\text{\,}\mathrm{V}$ powering the ASIC-FPGA communication [35]. The current consumption of the ASIC on the 1.2-V-line is not conveniently measurable, since this voltage ($1.2\text{\,}\mathrm{V}$) is generated locally on the ASIC test board (see Fig. 3). Here, a linear low-dropout (LDO) regulator with a negligible quiescent current $I_{q}$ is used and the internal circuits of that LDO are fed out of a different supply line. Hence, the average of the ASIC supply current $I_{\mathsf{DD12}}$ is basically identical to the average value of LDO input current $I_{\mathsf{DD}}$. This input current can be measured via a modification of the FED/D board. The FEB/D generates a pre-regulated voltage $U_{\mathsf{DD}}$ of $1.8\text{\,}\mathrm{V}$. This voltage is protected by a replaceable fuse F2. Exchanging this fuse with a shunt resistor $R$ allows to evaluate the current via measuring the voltage drop across this resistor. For our test, we used a shunt resistor of $0.13\text{\,}\mathrm{\SIUnitSymbolOhm}$ and captured the voltage drop $\Delta\bar{U}$ with an oscilloscope. Mathematical averaging reveals the average current. The output voltage of the LDO was confirmed to stay unaffected from the modification, i.e., the voltage drop across $R$ did not impact the output voltage regulation, which was stable at $1.2\text{\,}\mathrm{V}$. Hence, the power consumption $\bar{P}$ of the ASIC was then computed via

[TABLE]

in case a single ASIC board was connected to that very FEB/D channel. As visible in Fig. 3, a second ASIC board can be connected to the same output. In this case, the calculated power is hence the power for two ASICs. The introduced method only measures the ASIC power consumption due to operating the ASIC itself. The power consumption due to ASIC-FPGA communication is not included in the measured values, since it cannot be separated from other loads on the 2.5-V-line, e.g., the FPGA.

The three software configuration parameters $\mathsf{fe\_ib1}$, $\mathsf{fe\_ib2}$, and $\mathsf{disc\_sf\_bias}$ were successively changed to evaluate their impact on the power consumption. So far, only $I_{\mathsf{DD12}}$ as a function of $\mathsf{fe\_ib2}$ and $\mathsf{disc\_sf\_bias}$ is reported [35]. This study intends to provide a complete overview on the impact of the configuration parameters. The parameter $\mathsf{fe\_ib1}$ was changed from 0 to 60 in steps of $5\text{\,}$. The parameter $\mathsf{fe\_ib2}$ was changed from 0 to 30 in steps of $5\text{\,}$. The parameter $\mathsf{disc\_sf\_bias}$ was changed from 0 to 32 in steps of $4\text{\,}$. While one parameter was changed, the other two are kept at zero to reveal the influence of a that very parameter. For each setting, the respective power consumption was determined for data acquisition running in tot- or qdc-mode in single- and multi-channel experiments with FBK (NUV-HD) and KETEK PA3325-WB-0808 SiPMs and for acquiring dark counts or events of 22Na sources placed inside the setup. For all applied settings, data were acquired for $30\text{\,}\mathrm{s}$ at $16\text{\,}\mathrm{\SIUnitSymbolCelsius}$ ambient temperature. The overvoltage was set to $4.75\text{\,}\mathrm{V}$. The discriminator thresholds were kept constant at $\mathsf{vth\_t1}=20$, $\mathsf{vth\_t2}=20$, and $\mathsf{vth\_e}=15$. The minimum, default, and maximum power consumption of the ASIC was determined as benchmarks for further investigations. The corresponding parameter settings are $\mathsf{fe\_ib1}=60$, $\mathsf{fe\_ib2}=30$, and $\mathsf{disc\_sf\_bias}=32$ to reach minimum, $\mathsf{fe\_ib1}=59$, $\mathsf{fe\_ib2}=0$, and $\mathsf{disc\_sf\_bias}=0$ to reach default, and $\mathsf{fe\_ib1}=0$, $\mathsf{fe\_ib2}=0$, and $\mathsf{disc\_sf\_bias}=0$ to reach maximum power consumption. The settings for minimum and maximum power consumption were determined experimentally. The setting for default power consumption was extracted from the default ASIC software configuration.

Additionally, the impact of the power consumption setting on the ASIC performance was evaluated in coincidence experiments with two KETEK PA3325-WB-0808 SiPM arrays. For minimum, default, and maximum power consumption, the overvoltage was varied between $2.755.75\text{\,}\mathrm{V}$ in steps of $0.5\text{\,}\mathrm{V}$ with $\mathsf{vth\_t1}=30$, $\mathsf{vth\_t2}=20$, and $\mathsf{vth\_e}=15$. For each setting, data were acquired for $120\text{\,}\mathrm{s}$.

Employing Hamamatsu S14161-3050-HS-08 SiPM arrays, the influence on the dark count rate per channel was investigated. For this purpose, each channel was individually enabled to trigger only on the first discriminator $\mathsf{D\_T1}$ of the ASIC channel circuit. The validation by higher thresholds was disabled. For each setting, dark counts were acquired for $10\text{\,}\mathrm{s}$ at an overvoltage of $4.75\text{\,}\mathrm{V}$ and for discriminator thresholds between $\mathsf{vth\_t1}=1$ and $\mathsf{vth\_t1}=60$ in steps of 1.

III-B Setup calibration

A calibration according to the PETsys calibration routine [45] was run for each investigated SiPM type at default ASIC configuration with an overvoltage of $4\text{\,}\mathrm{V}$ and $\mathsf{vth\_t1}=20$, $\mathsf{vth\_t2}=20$, and $\mathsf{vth\_e}=15$. Investigating the impact of the power consumption on the ASIC performance and the dark count rate, a calibration was run at each power consumption setting.

III-C Data processing

Performance data were evaluated in the same manner as described in [49]: Data were prepared applying the PETsys routine $\mathsf{convert\_raw\_to\_singles}$ to convert raw data into single hit information. The obtained table containing a timestamp, an energy value, and a channel ID for each single hit registered was used for further processing. An energy value histogram was computed, where the peak positions of the two peaks in the 22Na spectrum ($511\text{\,}\mathrm{keV}$, $1274.5\text{\,}\mathrm{keV}$) were determined using a Gaussian fit routine. A saturation corrected model was fit to the determined positions, allowing to compute the energy in keV from the acquired energy values via

[TABLE]

Here, $E$ is the hit energy in keV and $e$ is the energy value in ADC units acquired for this hit. The factors $c$ and $s$ are a conversion factor and a saturation parameter determined by the fit routine. The energy resolution was determined as the full width at half maximum (FWHM) of the $511\text{\,}\mathrm{keV}$ peak in the converted energy spectrum. Single hits were checked for coincidences applying an energy filter of $400700\text{\,}\mathrm{keV}$ and a coincidence window of $7.5\text{\,}\mathrm{ns}$. For multi-channel data, the timestamps were corrected for the source positions. The coincidence time difference between two matched hits was computed. From the time difference histogram, the coincidence resolution time (CRT) was computed as the FWHM of the histogram peak. For each time difference histogram, the satellite peak fraction is computed. This fraction classifies all events matched as coincidences with a coincidence time difference larger than $2.5\text{\,}\mathrm{ns}$.

Performance results are stated dependent on the relative offset-corrected overvoltage \acUcorrel, which is computed via

[TABLE]

where \acUbd is the breakdown voltage of the employed SiPM, \acUbias is the applied bias voltage configured via the software, and \acUoff is the voltage offset between configured and actually applied bias that was determined by probing different ASIC channels. The voltage offset is due to a small DC voltage (approx. $750\text{\,}\mathrm{mV}$) at the input of each ASIC channel [51].

IV Results

IV-A Adjustability

The power consumption on the 1.2-V line changes for switching between system states (whole setup turned off, FEB/D booted, ASICs booted, measurement running, see Fig. 4). It stays constant during data acquisition, i.e., for the channel trigger circuit switching between different trigger states, and also between multiple measurements. Peaks visible when transferring the ASIC configuration for a new measurement (indicated by arrows in Fig. 4) are small compared to the total power consumption (approx. $6\text{\,}\mathrm{\char 37\relax}$ change).

In Fig. 5, we depict the influence of each of the three software configuration parameters $\mathsf{fe\_ib1}$, $\mathsf{fe\_ib2}$, and $\mathsf{disc\_sf\_bias}$ on the TOFPET2 ASIC power consumption in qdc-mode. In tot-mode, the acquired curves show the same shape. All parameters cause a drop of the power consumption when being increased. Here, the software configuration parameter $\mathsf{fe\_ib2}$, which, according to the data sheet [35], influences the discriminator noise, has the largest impact on the power consumption. The power consumption drops from $6.54.3\text{\,}\mathrm{mW/channel}$ for the acquisition of dark counts. The parameters $\mathsf{fe\_ib1}$ and $\mathsf{disc\_sf\_bias}$ have a lower impact on the power consumption. Here, the power consumption drops from $6.55.8\text{\,}\mathrm{mW/channel}$ and from $6.56.2\text{\,}\mathrm{mW/channel}$, respectively, for the acquisition of dark counts. No difference is visible between single- and multi-channel experiments. In these scans, we notice a systematic increase of the power consumption when configuring $\mathsf{fe\_ib1}>60$, i.e., $R_{\mathsf{IN}}>$32\text{,}\mathrm{\SIUnitSymbolOhm}$$ (see black circle in Fig. 5a). As a consequence, settings with $\mathsf{fe\_ib1}>60$ are excluded from further scans. If events of a radioactive source are acquired, a slight but systematic increase of the power consumption of approx. $0.5\text{\,}\mathrm{mW/channel}$ is visible. A shift of again approx. $0.2\text{\,}\mathrm{mW/channel}$ is visible if an SiPM array is connected to the ASIC test board instead of a single SiPM. Statistical errors of approx. $8\text{\,}\mathrm{\char 37\relax}$ mainly stemming from the resistance measurement are equally assumed on all measured data. As benchmarks for further investigations and for comparison with other ASIC models, the power consumption in qdc-mode is determined to be $3.6\text{\,}\mathrm{mW/channel}$ at its minimum, $6.4\text{\,}\mathrm{mW/channel}$ at its default, and $7.2\text{\,}\mathrm{mW/channel}$ at its maximum value (see Tab. I).

IV-B Analytical model

We assume that the power consumption per channel $P_{\mathsf{ch}}$ can be computed analytically prior to experimental determination by applying a model linearly superposing the observed effects for a given parameter tuple ($\mathsf{fe\_ib1}$, $\mathsf{fe\_ib2}$, $\mathsf{disc\_sf\_bias}$). To determine the model parameters, piece-wise defined functions are fit to the curves. A constant \acP0 is assumed that is set off against the allocated influence of the three parameters $\mathsf{fe\_ib1}$, written as \acdPfeib1, $\mathsf{fe\_ib2}$, written as \acdPfeib2, and $\mathsf{disc\_sf\_bias}$, written as \acdPdiscsfbias:

[TABLE]

We use linear or parabolic functions to model the impact of the respective parameters. When changing $\mathsf{disc\_sf\_bias}$ over its whole parameter range, the power consumption drops linearly (see Fig. 5c). Hence, \acdPdiscsfbias can be parameterized as

[TABLE]

For $\mathsf{fe\_ib1}$ and $\mathsf{fe\_ib2}$, the drop in power consumption is linear first, but becomes parabolic towards higher parameter values (see Fig. 5a and Fig. 5b). Therefore, the influence of $\mathsf{fe\_ib1}$ and $\mathsf{fe\_ib2}$ is parameterized as:

[TABLE]

[TABLE]

The model parameters $a_{i}$, $b_{i}$, and $f_{0}$ are determined using least-squares fit routine (see Tab. II). As $P_{0}$, i.e., the y-axis intercept of the power consumption curves in Fig. 5, shows a dependency on the count rate, it has to be determined experimentally setting $\mathsf{fe\_ib1}=0$, $\mathsf{fe\_ib2}=0$, and $\mathsf{disc\_sf\_bias}=0$.

In order to test this model, random tuples ($\mathsf{fe\_ib1}$, $\mathsf{fe\_ib2}$, $\mathsf{disc\_sf\_bias}$) are considered. The power consumption of the ASIC is measured for each tuple using the methods applied before and computed via the implemented model. The measured power consumption is plotted against the computed power consumption (see Fig. 6, blue dots). A linear regression is performed on the data points (see Fig. 6, red line). The linearity of the fit is determined to be 1.034 $\pm$ 0.018 with an y-axis intercept in the order of $0.1\text{\,}\mathrm{mW/channel}$.

IV-C Stability

The power consumption per channel is shown to be stable for overvoltages ranging from $0.75\text{\,}\mathrm{V}$ to $7.75\text{\,}\mathrm{V}$ at the three benchmark settings determined in prior measurements (see Fig. 8). In addition, the power consumption is stable for various count rates at the three benchmark settings (see Fig. 7). Neither different discriminator thresholds $\mathsf{vth\_t1}$ and different source distances nor changing numbers of ASIC channels enabled to trigger were observed to change the measured power consumption per channel significantly.

IV-D Impact on performance

The position of the $511\text{\,}\mathrm{keV}$ and $1274.5\text{\,}\mathrm{keV}$ peaks of the energy value spectra acquired via signal integration (qdc-mode) is affected by different power consumption settings as indicated by arrows in Fig. 9. The filtered count rate (counts with an energy between $400700\text{\,}\mathrm{keV}$) drops by approx. $10\text{\,}\mathrm{\char 37\relax}$ over the overvoltage range investigated (see Fig. 10c). The acquired filtered count rate does not change for different power consumption settings. Furthermore, a slight deterioration in energy resolution is observed in performance experiments (see Fig. 10b). In comparison to the default setting, systematic deviations smaller than $0.5\text{\,}\mathrm{\char 37\relax}$ (absolute change) are visible for the energy resolution at maximum and minimum power consumption for all applied overvoltages.

Adjusting the power consumption is shown to have a significant influence on the CRTs achieved in coincidence experiments (see Fig. 10a). At the cost of a higher consumption, CRTs can be improved by $2040\text{\,}\mathrm{ps}$ comparing the performance for different overvoltages at minimum and maximum power consumption configuration.

Additionally, a higher fraction of events contributing to the formation of satellite peaks in the coincidence time difference spectra is reported for a lower power consumption. The fraction increases by up to $3\text{\,}\mathrm{\char 37\relax}$ comparing the situation for minimum and maximum power consumption at different overvoltages (see Fig. 10d). Since prior studies showed that the satellite peak fraction depends on the configured trigger threshold of the first discriminator [49], the increased fraction calls for an adjustment of the trigger thresholds during performance experiments.

Additionally, the dark count rate was acquired for settings in the full range of possible thresholds $\mathsf{vth\_t1}$. Scanning the dark counts of an SiPM in qdc-mode results in acquiring the number of events, i.e., the number of SiPM pulses at and above a configured voltage threshold and, thus, can be used to adjust the trigger thresholds of the first discriminator. The dark count scans are expected to show plateaus indicating an increasing number of SPADs breaking down. In Fig. 11, these plateaus are visible in all curves acquired for each channel at the three benchmark settings. The acquired curves for the dark count rates of each channel are compressed for a higher power consumption and stretched out for a lower power consumption. The dark count rate is slightly increased for $\mathsf{vth\_t1}=1-10$ if configuring a higher power consumption (see Fig. 11). In this configuration, setting $\mathsf{vth\_t1}>10$ is sufficient to trigger on a higher number of photo-electrons. For minimum power consumption, this threshold has to be increased by a factor of 2.5 to reach the same trigger level.

V Discussion

The measured power consumption of $3.67.2\text{\,}\mathrm{mW/channel}$ only includes the power consumption due to the ASIC operation. An estimate of the power consumption due to the ASIC-FPGA communication can be computed taking an input current of $30\text{\,}\mathrm{mA}$ as a reference [35]. Considering a supply voltage of $2.5\text{\,}\mathrm{V}$ and 64 ASIC channels, a power consumption of approx. $1.2\text{\,}\mathrm{mW/channel}$ has to be added to the measured benchmarks. The obtained values are in good agreement with the power consumption of $58\text{\,}\mathrm{mW/channel}$ reported by PETsys Electronics S.A. [44].

Regarding the analytical model, which was implemented to compute the power consumption due to ASIC operation, the determined linearity of 1.034 $\pm$ 0.018 and a negligible y-axis intercept in the order of $0.1\text{\,}\mathrm{mW/channel}$ confirm that this model can be used to compute the power consumption prior to experiments and thus to select adequate settings. The model has only been verified for the present setup and should be tested on different benchtop setups. The parameter $P_{0}$ so far can only be determined experimentally. This parameter correctly accounts for the count rate dependency of the power consumption and thus, also would incorporate effects of changing the discriminator thresholds or applied overvoltage, and employing different SiPM types or scintillator topologies. It was shown that these changes do not significantly affect the stability of power consumption for a given SiPM configuration in multi-channel experiments. In addition, the introduced model assumes equal behavior of all parts of the ASIC circuit at each point in the three-dimensional parameter space of ($\mathsf{fe\_ib1}$, $\mathsf{fe\_ib2}$, $\mathsf{disc\_sf\_bias}$). Experiments probing the behavior of $\mathsf{fe\_ib1}$ for $\mathsf{fe\_ib2}$ or $\mathsf{disc\_sf\_bias}$ other than zero, as well as related experiments for the other two parameters, should be considered. However, since the minimum power consumption and various other tuples (see Fig. 6) are correctly described by the model, we do not expect changes to the behavior.

Compared to other ASICs the TOFPET2 ASIC features a similar or even lower power consumption. For other models with similar architecture, higher values are often reported, e.g., $10\text{\,}\mathrm{mW/channel}$ for the Triroc ASIC, $25\text{\,}\mathrm{mW/channel}$ for the STIC3 ASIC, and less than $40\text{\,}\mathrm{mW/channel}$ for the PETA4 ASIC [22, 23, 20]. The prior version of the TOFPET2 ASIC also featured a slightly higher power consumption ($811\text{\,}\mathrm{mW/channel}$) [34]. A lower power consumption of $3.5\text{\,}\mathrm{mW/channel}$ reported for the Petiroc ASIC does not include the power consumption of the ASIC buffers [19]. The new version of the FlexToT ASIC, the HRFlexToT ASIC, also comes along with a low power consumption of $3.5\text{\,}\mathrm{mW/channel}$ [27]. The Petiroc, the NINO, the FlexToT and the HRFlexToT ASIC do not employ TDCs inside the ASIC circuit, which results in the reported very low power consumptions. Table III provides an overview over the given values and the single-channel performance reported along with these. Due to varying scintillator heights, it is not possible to confirm a clear trend showing a better performance for a higher power consumption. Comparative studies between different ASIC models, e.g., the FlexToT ASIC ($11\text{\,}\mathrm{mW/channel}$) and the NINO ASIC ($27\text{\,}\mathrm{mW/channel}$) [52] show that apart from a comparison of the power consumption, multiple parameters, such as linearity of the energy measurement, timing performance as well as the ease of system integration, have to be considered to choose the digitization circuit for a specific application.

The pre-amplifier is a low-impedance current conveyor [47]. In current-sensing, a low input stage impedance resulting in fast pulses is beneficial for the timing resolution [33]. In contrast a higher input stage impedance results in the slower and higher rise of the acquired pulses. This behavior is reflected by the performance scans conducted for different configurations of the power consumption. The systematic change in energy resolution visible in performance experiments depending on the power consumption configuration is suspected to be due to the changed pulse shape for a different input stage impedance. The acquired dynamic range of the energy spectra does not call for any gain adjustments. As the filtered count rate does not change between different settings, the observed shift of the 511-keV peak in the energy value spectra does not lead to a loss of events due to the applied energy filter. The observed CRT deterioration can be explained referring to the increased input impedance when configuring the ASIC to have a lower power consumption. Due to a slower rise of the registered SiPM signals, the ASIC triggers on these signals at a later point in time, resulting in worse CRTs. In addition, a shift of the SiPM operation point due to changing the ASIC configuration is visible in the acquired CRT curves, which do not reach a clear minimum for maximum power consumption (see Fig. 10a). Low-power ASICs found in literature also show a worse performance than other ASIC models with a higher power consumption [59]. However, since the TOFPET2 trigger circuit is capable of rejecting noise events, the TOFPET2 ASIC still delivers CRTs down to $300\text{\,}\mathrm{ps}$ at $3.6\text{\,}\mathrm{mW/channel}$ power consumption, which is only a $20\text{\,}\mathrm{ps}$ performance loss compared to the default setting.

The dark count scans imply that the acquired dark count rate and, accordingly, the photo-electron trigger level is influenced by the configuration of the power consumption, if the trigger threshold is kept at a constant level. This matches the observation of a higher satellite peak fraction at lower power consumption. The level to trigger between the first and second or the second and third photo-electron is shifted to higher thresholds. One has to keep in mind that the acquired dark count rate is influenced by the intrinsic radioactivity of the scintillator coupled to the SiPM array. Considering an LYSO activity of $500\text{\,}\mathrm{Bq}\text{\,}{\mathrm{cm}}^{-3}$ [60] and assuming that each decay is acquired as valid event, the LYSO contribution to the acquired dark count rate would add up to $0.006\text{\,}\mathrm{kcps}\text{\,}{\mathrm{mm}}^{-2}$. This contribution should only be visible as a constant offset in the acquired dark count rate. Hence it does not contribute to the observed shift of the photo-electron trigger levels. The effect of shifted trigger levels is probably based on the entire signal processing chain and so far cannot be attributed to one of the parameters changed. The shift is stronger visible between the default and minimum setting, where multiple parameters were changed. It can be assumed that the input stage impedance modifies the voltage pulse height and hence, the photo-electron trigger level, since only the parameter $\mathsf{fe\_ib1}$, i.e., the input stage impedance $\mathsf{R_{IN}}$, was changed between the maximum and default configuration (default $\mathsf{R_{IN}}=$ $27\text{\,}\mathrm{\SIUnitSymbolOhm}$, maximum $\mathsf{R_{IN}}=$ $10\text{\,}\mathrm{\SIUnitSymbolOhm}$).

VI Conclusion

The TOFPET2 ASIC features a power consumption ranging from $3.67.2\text{\,}\mathrm{mW/channel}$. Including an estimate of the power consumption due to ASIC-FPGA communication, these values increase to $4.88.4\text{\,}\mathrm{mW/channel}$ and are to our knowledge low compared to the power consumption of other ASIC models. The reported values are in good agreement with the specifications made by PETsys Electronics S.A.. We present an analytical model allowing the calculation of the power consumption prior to experiments. The power consumption is shown to be stable for a range of overvoltages and various count rates ranging from $1\text{\,}\mathrm{kcps}$ to $100\,000\text{\,}\mathrm{kcps}$. Thus, the power consumption remains sufficiently low under various measurement conditions to consider the ASIC for integration in a PET system.

As expected, the input stage impedance and discriminator noise have a significant influence on the ASIC performance. Depending on the configuration and applied overvoltages, achieved CRTs can be improved by $2040\text{\,}\mathrm{ps}$. For settings apart from the default setting, the energy resolution is deteriorated by up to $0.5\text{\,}\mathrm{\char 37\relax}$ (absolute deterioration). Configuring a lower power consumption results in a shift of the photo-electron trigger levels over the discriminator threshold range. Therefore, adjustments of the trigger threshold $\mathsf{vth\_t1}$ applied in performance scans are required. Combining a low power consumption of about $6.4\text{\,}\mathrm{mW/channel}$ with approx. $280\text{\,}\mathrm{ps}$ CRT and approx. $10.5\text{\,}\mathrm{\char 37\relax}$ energy resolution at default configuration, the TOFPET2 ASIC stands out as a promising candidate for future system developments.

VII Outlook

Investigations regarding the adjustments of the trigger threshold $\mathsf{vth\_t1}$ are necessary to deal with the changed photo-electron levels and to provide a fair comparison between the ASIC performance at different power consumption settings. In addition, a method to separate the loads on the 2.5-V-line needs to be developed to measure the power consumption due to the ASIC-FPGA communication and verify the given estimate. Since the TOFPET2 ASIC shows not only promising performance, but also low power consumption, it will be further favored for building an MR-compatible TOF-PET insert. To evaluate the MR-compatibility of the TOFPET2 ASIC we propose similar test protocols as applied in [61, 62].

VIII Acknowledgments

We thank Ricardo Bugalho and Luis Ferramacho from PETsys Electronics S.A. for kindly answering our many questions.