Cache Optimization for Memory Intensive Workloads on Multi-socket Multi-core servers

TL;DR

This paper proposes a cache optimization technique for multi-socket multi-core servers that reduces remote DRAM accesses by biasing cache replacement policies, thereby improving overall system performance.

Contribution

It introduces a cache management strategy that tracks and biases remote DRAM cache lines to minimize remote memory accesses in multi-socket systems.

Findings

Reduces remote DRAM cache misses

Improves server performance

Provides design details and qualitative comparison

Abstract

Major chip manufacturers have all introduced multicore microprocessors. Multi-socket systems built from these processors are used for running various server applications. Depending on the application that is run on the system, remote memory accesses can impact overall performance. This paper presents a cache optimization that can cut down remote DRAM accesses. By keeping track of remote cache lines loaded from remote DRAM and by biasing the cache replacement policy towards such remote DRAM cache lines the number of cache misses are reduced. This in turn results in improvement of overall performance. I present the design details in this paper. I do a qualitative comparison of various solutions to the problem of performance impact of remote DRAM accesses. This work can be extended by doing a quantitative evaluation and by further refining cache optimization.