# Bias current dependence of superconducting transition temperature in   superconducting spin valve nanowires

**Authors:** Alejandro A. Jara, Evan Moen, Oriol T. Valls, and Ilya N. Krivorotov

arXiv: 1908.03612 · 2019-11-27

## TL;DR

This study investigates how bias current influences the superconducting transition temperature in superconducting spin valve nanowires, revealing a sign change in the spin switch effect due to spin Hall currents, with implications for nanoscale superconducting devices.

## Contribution

It provides the first experimental evidence of bias current affecting the spin switch effect in superconducting nanowires, highlighting the role of spin Hall currents in this process.

## Key findings

- T_c(π) - T_c(0) changes sign with increasing bias current.
- Bias current influences the spin switch effect via spin Hall currents.
- Implications for nanoscale superconducting device design.

## Abstract

Competition between superconducting and ferromagnetic ordering at interfaces between ferromagnets (F) and superconductors (S) gives rise to several proximity effects such as odd-triplet superconductivity and spin-polarized supercurrents. A prominent example of an S/F proximity effect is the spin switch effect (SSE) observed in S/F/N/F superconducting spin-valve multilayers, in which the superconducting transition temperature T$_c$ is controlled by the angle $\phi$ between the magnetic moments of the F layers separated by a nonmagnetic metallic spacer N. Here we present an experimental study of SSE in Nb/Co/Cu/Co/CoO$_x$ nanowires measured as a function of bias current flowing in the plane of the layers. These measurements reveal an unexpected dependence of T$_c(\phi)$ on the bias current: T$_c(\pi)$--T$_c(0)$ changes sign with increasing current bias. We attribute the origin of this bias dependence of the SSE to a spin Hall current flowing perpendicular to the plane of the multilayer, which suppresses T$_c$ of the multilayer. The bias dependence of SSE can be important for hybrid F/S devices such as those used in cryogenic memory for superconducting computers as device dimensions are scaled down to the nanometer length scale.

## Full text

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## Figures

3 figures with captions in the complete paper: https://tomesphere.com/paper/1908.03612/full.md

## References

58 references — full list in the complete paper: https://tomesphere.com/paper/1908.03612/full.md

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Source: https://tomesphere.com/paper/1908.03612