High-Level Combined Deterministic and Pseudoexhuastive Test Generation for RISC Processors

TL;DR

This paper introduces a high-level, implementation-independent test generation method for RISC processors that combines deterministic control tests with pseudoexhaustive data tests, improving fault coverage and testing efficiency.

Contribution

It proposes a novel high-level control fault model and a combined test generation approach that enhances fault coverage for RISC processor testing.

Findings

High efficiency of generated test programs demonstrated on miniMIPS processor.

The high-level control fault model covers larger fault classes including multiple faults.

Effective combination of deterministic and pseudoexhaustive testing improves test quality.

Abstract

Recent safety standards set stringent requirements for the target fault coverage in embedded microprocessors, with the objective to guarantee robustness and functional safety of the critical electronic systems. This motivates the need for improving the quality of test generation for microprocessors. A new high-level implementation-independent test generation method for RISC processors is proposed. The set of instructions of the processor is partitioned nto groups. For each group, a dedicated test template is created, to be used for generating two test programs, for testing the control and the data paths respectively. For testing the control part, a novel high-level control fault model is proposed. Using this model, a set of deterministic test data operands are generated for each instruction of the given group. The advantage of the high-level fault model is that it covers larger than SAF fault class including multiple fault coverage in the control part. For generating the data path test, pseudoexhaustive data operands are used. We investigated the feasibility of the approach and demonstrated high efficiency of the generated test programs for testing the execute module of the miniMIPS RISC processor.