Simulation of temperature profile for the electron- and the lattice-systems in laterally structured layered conductors

TL;DR

This paper presents a simulation method to analyze the temperature profiles of electrons and the lattice in layered conductors, revealing significant hot spots and differences between semiconductor and metal conductors due to specific heat variations.

Contribution

It introduces a novel simulation approach that separately models electron and lattice subsystems in layered conductors, enabling detailed analysis of nonequilibrium thermal dynamics.

Findings

Hot electron generation causes hot spots at inner corners.

Electron temperature hot spots are sharper and hotter than lattice hot spots.

Differences in hot spot profiles between semiconductor and metal are mainly due to specific heat differences.

Abstract

Electrons in operating microelectronic semiconductor devices are accelerated by locally varying strong electric field to acquire effective electron temperatures nonuniformly distributing in nanoscales and largely exceeding the temperature of host crystal lattice. The thermal dynamics of electrons and the lattice are hence nontrivial and its understanding at nanoscales is decisively important for gaining higher device performance. Here, we propose and demonstrate that in layered conductors nonequilibrium nature between the electrons and the lattice can be explicitly pursued by simulating the conducting layer by separating it into two physical sheets representing, respectively, the electron- and the lattice-subsystems. We take, as an example of simulating GaAs devices, a 35nm thick 1um wide U-shaped conducting channel with 15nm radius of curvature at the inner corner of the U-shaped bend, and find a remarkable hot spot to develop due to hot electron generation at the inner corner. The hot spot in terms of the electron temperature achieves a significantly higher temperature and is of far sharper spatial distribution when compared to the hot spot in terms of the lattice temperature. Similar simulation calculation made on a metal (NiCr) narrow lead of the similar geometry shows that a hot spot shows up as well at the inner corner, but its strength and the spatial profiles are largely different from those in semiconductor devices. The remarkable difference between the semiconductor and the metal is interpreted to be due to the large difference in the electron specific heat, rather than the difference in the electron phonon interaction. This work will provide useful hints to deeper understanding of the nonequilibrium properties of electrical conductors, through a simple and convenient method for modeling nonequilibrium layered conductors.

Tables

Table 1. Table 1: Parameters used in the simulation.

Quantity	${\sigma }_e$	${\kappa }_e$	${\kappa }_L$	$h_{e-ph}$	$h_I$	${\kappa }_S$
Unit	$S/m$	$W/\left(m\cdot K\right)$	$W/\left(m\cdot K\right)$	$K{m}^2/W$	$K{m}^2/W$	$W/\left(m\cdot K\right)$
n-GaAs	$8.8\times {10}^4$	0.1	50	$4.3\times {10}^{-7}$	0	50
NiCr	$2.89\times {10}^5$	15	1	$2.7\times {10}^{-10}$	$3\times {10}^{-8}$	150

Equations

$$P_{e-ph}=(T_e-T_L)C_e/{\tau }_{e-ph}$$

$$h_{e-ph}={\tau }_{e-ph}/C_e.$$

$$C_e=C_{ec}=(3/2)N_{2D}{k}_B,$$

$$C_e=C_{eF}=\{(3/2)k_B{T}_e/{\epsilon }_F\}{C}_{ec}$$

$$T_e-T_L=({\tau }_{e-ph}/C_e)P=h_{e-ph}P$$

Full text

1 Introduction

Electro-thermal behavior is a key ingredient for understanding charge carrier transport phenomena in semiconductor devices including two-dimensional (2D) materials, hetero Junctions, and strong correlated systems [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]. In small devices on nanoscales, hot electron generation and the resulting characteristic interaction with the host crystal lattice (or phonons) complicates the electro-thermal analysis and limits the device performance [16, 17]. Whereas knowing the detailed local profile of the electron effective temperature, $T_{e}$, separately from that of the lattice temperature, $T_{L}$, in the presence of current is prerequisite for understanding the transport characteristics on nanoscales [18, 19, 20, 21, 22],$T_{e}$ has been experimentally hardly accessible [23, 24, 25, 26, 27, 28, 29, 30, 31] until quite recently [32, 33]. It follows that the study of electro-thermal properties has so far been restricted only to the simulation methods such as those of Monte Carlo (MC) simulation based on the Boltzmann transport equations, hydrodynamic equations or molecular dynamics [34, 35, 36, 37, 38]. Unfortunately, however, MC simulations comprise involved calculation procedures, which are not necessarily convenient to gain intuitive understanding of the electro-thermal transport phenomena of given devices. On the other hand, the nonequilibrium condition cannot be incorporated in commercially available semiconductor device simulators.

Here, we propose a simplified electro-thermal model for layered conductors on the basis of the assumption that the electron- and the lattice-subsystems are, respectively, in quasi-equilibrium states characterized by the effective electron temperature $T_{e}$ and the lattice temperature $T_{L}$. The model is applied to a U-shaped layered conductor, where electric field is concentrated at the inner corner of the U-shaped bend. In a semicodncuctor device, simulating GaAs, remarkable hot electron distribution ($T_{e}\gg T_{L}$) is found to develop at the corner, forming a sharp hot spot with $T_{e}$ reaching $\sim 2000K$. Differently, in metal devices, simulating NiCr, hot electron effects are found to be absent ($T_{e}\approx T_{L}$), whereas a hot spot profile is visible. These findings are consistent with recent experimental results reported on metals [39] and semiconductors [32], indicating the validity of the present model for simulating the electro-thermal behavior of layered conductors in nonequilibrium conditions.

2 Simulation model

Figure 1 describes the model conductor considered in this study. A layered conductor with the electric conductivity $\sigma_{e}$ is deposited on an insulating substrate, which is anchored by the heat sink at 300K. The lateral shape of the conductor is arbitrary, so that the electric field $\mathbf{E}$, the current density $\mathbf{j}$, the electron temperature $T_{e}$ and the lattice temperature $T_{L}$ in the conductor are variables to be consistently derived as functions of the lateral position $\mathbf{r}$ for a given conductor with a given bias voltage. In the conductor electrons gain energy from $\mathbf{E}$ through $P=\mathbf{j}(\mathbf{r})\cdot\mathbf{E}(\mathbf{r})=\sigma_{e}E^{2}$ and the energy gained from the field is, in turn, released to the lattice via electron phonon interaction, characterized by the electron-phonon energy relaxation time $\tau_{e-ph}$. The excess energy (or heat) of electrons is transferred, as well, within the electron system through the electron thermal conduction $-\kappa_{e}\bigtriangledown T_{e}$ with $\kappa_{e}$ the electron thermal conductivity. The heat is transferred similarly within the lattice system through lattice thermal conduction $-\kappa_{L}\bigtriangledown T_{L}$ with $\kappa_{L}$ the lattice thermal conductivity. The heat is eventually transferred to the substrate $(T_{L}-T_{LS})/h_{I}$ with $h_{I}$ being the interface thermal resistance and $T_{LS}(\mathbf{r})$ the local lattice temperature of the substrate on its top surface, and finally absorbed by the heat sink. Heat is transferred as well through electrical leads connected to the conductor, as represented by the arrows marked with $\kappa_{e}$ and $\kappa_{L}$ in fig.1 (c), which is taken into account in the model through an appropriate boundary condition as mentioned below for fig.2 (a).

As schematically shown in figs.1 (b) and (c), our model represents the energy transfer from the electron system to the lattice system in the conductor by the interface heat transfer between the electron sublayer at $T_{e}$ to the lattice sublayer at $T_{L}$. The energy flux released from the electron system to the lattice system through the electron phonon interaction is given by

[TABLE]

with $C_{e}$ the electron specific heat per unit area, so that the effective interface thermal resistance $h_{e-ph}$ is

[TABLE]

The specific heat is approximated by

[TABLE]

for a classical electron system ($k_{B}T_{e}\gg\varepsilon_{F}$) and by

[TABLE]

for an electron system with the Fermi energy $\varepsilon_{F}$ much higher than the thermal energy ($k_{B}T_{e}\ll\varepsilon_{F}$). Here, $k_{B}$ is the Boltzmann constant, and $N_{2D}$ is the 2D electron density.

3 Simulated structure

As schematically illustrated in fig.2 (a), we consider a 35nm thick conductor layer shaped into a $1\mu m$-wide U-shaped channel with the radius of inner curvature of the U-shape is 15nm and the gap between the channels is $S=30nm$. For the simulation, the electron- and the lattice-systems of the conducting channel are separately represented by Layers A and B, where Layer B is placed on the $10\mu m$-thick substrate (Layer C). The boundary condition of temperature is given by assuming $T=300K$ on the bottom face Layer C and on the end faces of Layers A and B as marked by the orange lines in fig.2 (a). As to the bias condition, a constant voltage is assumed on each end face of the conducting channel (Layer A), and a bias voltage $V_{b}$ is assumed to give the voltage difference between the two end faces.

Two different conductors are considered. One is a doped n-GaAs channel and the other is a NiCr channel, similar to those studied, respectively, in Refs.32 and 39. Substrates are assumed to be lattice-matched GaAs/AlGaAs for n-GaAs sample [32] and single crystal Si covered with a thin $SiO_{2}$ layer for NiCr sample [39]. The electron density in n-GaAs and NiCr samples are, respectively, $N_{3D}=3.3\times 10^{24}/m^{3}$ and $1.0\times 10^{30}/m^{3}$; in terms of the sheet electron density, $N_{2D}=1.1\times 10^{17}/m^{2}$ and $3.5\times 10^{22}/m^{2}$. The specific heat is taken to be $C_{e}=2.3\times 10^{-6}Ws/(Km^{2})$ and $1.1\times 10^{-2}Ws/(Km^{2})$, respectively assuming Eqs. (3) and (4) for n-GaAs and NiCr samples. In n-GaAs sample, the interface thermal resistance ($h_{I}$) is negligibly small because the n-GaAs conducting layer is epitaxially grown on the lattice matched substrate. The electron-phonon energy relaxation time is assumed to be $\tau_{e-ph}=1ps$ and 3ps, respectively for n-GaAs [32] and NiCr [39]. Parameter values used are summarized in Table 1.

4 Results and discussions

Joule heating caused by electric field and thermal conduction generated by temperature gradient or difference are consistently treated by using a commercial multiphysics software (COMSOL), where the bias voltage is taken to be $V_{b}=4.5V$ in all the calculations described below. It is a common feature of both n-GaAs and NiCr samples that the electric field is concentrated around the U-shaped inner corner as exemplified by the result for n-GaAs sample: Electric field is nearly uniform and $E=2\sim 3kV/cm$ in a region away from the U-shaped corner, but rapidly increases to reach about $E=10kV/cm$ in the vicinity of the U-shaped inner corner. As a consequence of this $E$-field enhancement, remarkable nonuniform hot-electron distribution is found to be generated at the inner corner of the n-GaAs sample as shown in fig.2 (c). While the trend of the $E$-field enhancement is substantially the same in the NiCr sample, resulting temperature distribution in the electron- and the lattice-systems is largely different as described in detail below.

Figures 3 (a), (b) and figures 4 (a)-(d) display the distributions of $T_{e}$ (Layer A) and $T_{L}$ (Layers B) for the NiCr sample. The profile of $T_{e}$ is similar to that of $T_{L}$, and both exhibit spatially varying heating in accord with the $E$-field enhancement peaked at the U-shaped inner corner. The highest temperature at the hot spot is about $150^{\circ}$C above the heat sink (300K). The amplitude of the temperature rise at the hot spot ($\bigtriangleup T_{e}\approx 150^{\circ}$C) as well as the quasi-equilibrium feature between the electron- and the lattice-systems ($T_{e}\approx T_{L}$) substantially reproduce the experimental findings reported in Ref.39.

The feature of the hot spot formation is largely different in the n-GaAs sample as shown in figs.3 (c)(d) and figs.4 (e)-(h). The electron temperature $T_{e}$ is much higher than the lattice temperature $T_{L}$, indicating nonequilibrium hot electron generation, and it assumes a very sharp prominent peak reaching as high a value as $T_{e}\sim 2000K$. On the other hand, the highest value of $T_{L}$ ($<330K$) is at most only $\sim 30^{\circ}$C above the temperature of the heat sink (300K). In addition, the hot-spot feature is practically missing as evident in figs.4 (f) and (h). The generation of remarkable hot electron distribution is consistent with the experimental finding reported on n-GaAs constriction devices [32].

The large difference in the electro-thermal properties noted between the n-GaAs sample and the NiCr sample in this study is suggested to be generally inherent to semiconductors and metals. When energy flux $P$ is fed to the electron system in a steady state, the electrons are heated above the lattice temperature by

[TABLE]

if temperature gradient is ignored. For a given $P$, the rise of $T_{e}$ is proportional to $\tau_{e-ph}$, and $1/C_{e}$. In general, $\tau_{e-ph}$ is not largely different between semiconductors and metals, but the heat capacity $C_{e}$ is by orders of magnitude smaller in semiconductors because the electron density is far lower. It follows that the electron system is readily driven away from the equilibrium with lattice in semiconductors. In terms of our model ($h_{e-ph}$), thermal contact between the electron- and the lattice-systems are weak in semiconductors so that they are readily driven out of equilibrium. We mention that a high mobility of electrons is often ascribed to be the cause of hot electron generation in semiconductors. The present study makes this assumption questionable; namely, a high mobility implies a high electrical conductivity (and a large $P$), but the electrical conductivity is usually higher in metals and does not explain why semiconductor is more feasible for hot electron generation.

In this study simulation calculation assumed linear transport. Namely the electrical conductivity and the thermal conductivities are assumed to be constants. In metals, nonlinear effects may not be significant since the $T_{e}$ rise is not too large. In the doped n-GaAs sample at room temperature (as in this work), nonlinear effects may not be serious up to $E\approx 10kV$ [32], so that the findings in the present study are supposed to be valid. In the higher $E$ region above $10kV/cm$, however, the electron mobility will be reduced due to the transfer of electrons to upper (X and/or L) valleys. Even in such a higher-$E$ region, our model will provide a useful guideline at the starting point.

5 Summary

We demonstrate that in layered conductors nonequilibrium nature between the electrons and the lattice can be explicitly pursued by separating the electron- and the lattice-subsystems into two physical layers that exchange heat at the interface. Highly nonequilibrium distribution of electrons from that of the lattice is found in a doped n-GaAs sample. In a NiCr sample with a similar configuration, the electron- and the lattice-systems are in quasi-equilibrium. Remarkable difference of the electro-thermal properties of semiconductors and metals is suggested to arise from the difference in the electron specific heat. This work provides a simple and convenient method for modeling layered conductors in a nonequilibrium condition, and will give useful hints for deeper understanding of the nonequilibrium properties of electrical conductors

Acknowledgements.

We acknowledge funding support from National Key Research Program of China under grant No. 2016YFA0302000, National Natural Science Foundation of China under grant Nos. 11674070/11427807/11634012, and Shanghai Science and Technology Committee under grant Nos.18JC1420402, 18JC1410300, 16JC1400400. S.K. acknowledges support by the Chinese Academy of Sciences Visiting Professorships for Senior International Scientists.