Gate Leakage Suppression and Breakdown Voltage Enhancement in p-GaN HEMTs using Metal/Graphene Gates

TL;DR

This paper demonstrates that inserting graphene layers in p-GaN HEMTs significantly enhances performance by increasing the on/off ratio, raising the threshold voltage, reducing leakage, and improving breakdown voltage and thermal stability.

Contribution

The study introduces a novel graphene gate insertion technique that improves the electrical and thermal performance of p-GaN HEMTs, including achieving the first reported breakdown voltage for Schottky gate p-GaN HEMTs.

Findings

Ion/Ioff ratio increased by 50 times

Gate leakage reduced by 50 times

Breakdown voltage of 12.1 V achieved after annealing

Abstract

In this work, single-layer intrinsic and fluorinated graphene were investigated as gate insertion layers in normally-OFF p-GaN gate HEMTs, which wraps around the bottom of the gate forming Ti/graphene/p-GaN at the bottom and Ti/graphene/ SiNx on the two sides. Compared to the Au/Ti/p-GaN HEMTs without graphene, the insertion of graphene can increase the ION/IOFF ratios by a factor of 50, increase the VTH by 0.30 V and reduce the off-state gate leakage by 50 times. Additionally, this novel gate structure has better thermal stability. After thermal annealing at 350 {\deg}C, gate breakdown voltage holds at 12.1 V, which is first reported for Schottky gate p-GaN HEMTs. This is considered to be a result of the 0.24 eV increase in Schottky barrier height and the better quality of the Ti/graphene/p-GaN and Ti/graphene/SiNx interfaces. This approach is very effective in improving the Ion/Iff ratio and gate BV of normally-OFF GaN HEMTs.