Silicon Hard-Stop Spacers for 3D Integration of Superconducting Qubits

TL;DR

This paper introduces silicon hard-stop spacers for 3D integration of superconducting qubits, improving chip planarity and maintaining high qubit coherence, enabling more complex quantum circuit designs.

Contribution

It demonstrates a novel silicon spacer fabrication method compatible with superconducting qubit processes, ensuring precise chip spacing without degrading device performance.

Findings

High-quality resonators on etched silicon surfaces

Qubit coherence times exceeding 40 microseconds near spacers

Successful integration of spacers with existing qubit fabrication processes

Abstract

As designs for superconducting qubits become more complex, 3D integration of two or more vertically bonded chips will become necessary to enable increased density and connectivity. Precise control of the spacing between these chips is required for accurate prediction of circuit performance. In this paper, we demonstrate an improvement in the planarity of bonded superconducting qubit chips while retaining device performance by utilizing hard-stop silicon spacer posts. These silicon spacers are defined by etching several microns into a silicon substrate and are compatible with 3D-integrated qubit fabrication. This includes fabrication of Josephson junctions, superconducting air-bridge crossovers, underbump metallization and indium bumps. To qualify the integrated process, we demonstrate high-quality factor resonators on the etched surface and measure qubit coherence (T1, T2,echo > 40 {\mu}s) in the presence of silicon posts as near as 350 {\mu}m to the qubit.