Performance Comparison of Quasi-Delay-Insensitive Asynchronous Adders

TL;DR

This paper compares various quasi-delay-insensitive asynchronous adders in terms of design metrics, highlighting their suitability for low power and area-constrained VLSI applications.

Contribution

It provides a detailed comparison of different QDI adder architectures, identifying those optimal for low power and area efficiency in 32/28nm CMOS technology.

Findings

Identifies QDI adders suitable for low power applications

Highlights design metrics differences among QDI architectures

Excludes non-QDI adders due to lack of robustness

Abstract

In this technical note, we provide a comparison of the design metrics of various quasi-delay-insensitive (QDI) asynchronous adders, where the adders correspond to diverse architectures. QDI adders are robust, and the objective of this technical note is to point to those QDI adders which are suitable for low power/energy and less area. This information could be valuable for a resource-constrained low power VLSI design scenario. Non-QDI adders are excluded from the comparison since they are not robust although they may have optimized design metrics. All the QDI adders were realized using a 32/28nm CMOS process.