All-Analog Adaptive Equalizer for Coherent Data Center Interconnects

TL;DR

This paper introduces the first all-analog adaptive equalizer for coherent optical data center interconnects, demonstrating reduced power consumption and complexity compared to digital solutions at 40 Gb/s over 10 km fiber.

Contribution

It presents a novel all-analog adaptive equalizer architecture using the constant modulus algorithm, implemented in 130 nm SiGe BiCMOS technology for the first time.

Findings

Successfully demonstrated 40 Gb/s data processing over 10 km fiber.

Achieved blind adaptation of the equalizer in the analog domain.

Showed potential for lower power consumption in advanced CMOS technologies.

Abstract

In a high-speed coherent optical transmission system, typically the signals obtained at the receiver front-end are digitized using very high-speed ADCs and then processed in the digital domain to remove optical channel impairments. In this work, we show that these signals can instead be processed in the analog domain itself, which can significantly reduce the power consumption as well as the complexity of the receiver. The first all-analog adaptive equalizer for receivers of coherent dual-polarization optical links has been presented with its detailed architecture and measurement results. The proof-of-concept equalizer uses the constant modulus algorithm for blind adaptation of its weight coefficients to implement a 4x4 2-tap FIR filter in 130 nm SiGe BiCMOS technology. Its functionality is evaluated experimentally for 40 Gb /s data rate and 10 km standard single-mode fiber channel. This demonstration shows that the use of all-analog processing for short-reach data-center interconnects is feasible and is a much simpler solution than the use of the high-speed ADC+DSP based approach. Moreover, when implemented in advanced CMOS or FinFET technologies, the power consumption of the equalizer is expected to be significantly lower than the DSP based implementations in similar process technologies.

Figures

Equations

$$x_{eq}={\mathbf{h}}_{xx}^T\mathbf{x}+{\mathbf{h}}_{xy}^T\mathbf{y},y_{eq}={\mathbf{h}}_{yx}^T\mathbf{x}+{\mathbf{h}}_{yy}^T\mathbf{y},$$

$$h_{xx,k}(t)=\beta {\int }_0^t{x}_{eq}(\tau )[1-|x_{eq}(\tau ){|}^2]x(\tau -k{\tau }_d)d\tau ,$$

$$h_{xy,k}(t)=\beta {\int }_0^t{y}_{eq}(\tau )[1-|y_{eq}(\tau ){|}^2]x(\tau -k{\tau }_d)d\tau ,$$

$$h_{yx,k}(t)=\beta {\int }_0^t{x}_{eq}(\tau )[1-|x_{eq}(\tau ){|}^2]y(\tau -k{\tau }_d)d\tau ,$$

$$h_{yy,k}(t)=\beta {\int }_0^t{y}_{eq}(\tau )[1-|y_{eq}(\tau ){|}^2]y(\tau -k{\tau }_d)d\tau ,$$

$$EVM(\%)=\frac{\sqrt{\frac{1}{N}\sum _{k=1}^N\left\{(I_k-\widehat{I_k}{)}^2+(Q_k-\widehat{Q_k}{)}^2\right\}}}{A}\times 100\%$$

$$BER\approx\frac{2(1-1/P)}{\log_{2}P}Q\left\{\sqrt{\bigg{(}\frac{3\log_{2}P}{P^{2}-1}\bigg{)}\bigg{(}\frac{2}{EVM^{2}\log_{2}M}\bigg{)}}\right\}$$

Full text

I Introduction

Data center interconnects (DCIs) are expected to carry around 80% of the global Internet traffic, which is estimated to increase two-fold from today’s traffic of 200 EB/month, by 2022 [1, 2]. To support the increased traffic, DCI interface speeds are projected to cross 1.6 Tb/s in the near future [3]. To meet the current needs, 4-level pulse amplitude modulation (PAM-4) format based intensity modulation-direct detection (IMDD) transceivers with electronics operating at 56 GBd are being standardized [4, 3]. However, IMDD techniques are anticipated to give way to the transmission of more spectrally efficient modulation formats through single-mode fiber (SMF) in short-reach links [5, 6], mainly due to data rate scalability limitations [7]. As opposed to IMDD, coherent techniques aid in achieving data rate scalability along with a better receiver sensitivity [8]. Coherent links that use higher order modulation formats and polarization multiplexing help to achieve higher capacities and longer channel lengths, relying heavily on digital signal processing (DSP) to overcome the impairments added by the fiber channel. However, such links require high-speed, high-precision analog-to-digital converters (ADCs) to digitize the received signals after optical-to-electrical (O/E) conversion followed by high-speed DSP. Therefore, usage of the ADC+DSP approach becomes prohibitive for DCIs due to a huge amount of power consumption and complexity involved in this solution [9].

To overcome this issue an analog domain processing based receiver was first proposed in our previous work [10]. Schematic level circuit simulations results of the receiver were presented in [11] and the low-speed measurement results of an equalizer chip for the receiver were presented in [12]. Since then a few other solutions using analog signal processing (ASP) for coherent optical links were reported[13, 14, 9, 15, 16, 17]. For example, [13] discusses an analytical study on the feasibility of DSP-free homodyne dual-polarization quadrature phase-shift keying (DP-QPSK) receivers for DCIs. The reported architecture uses a simplified $2\times 2$ equalizer, to correct small amounts of dispersion and bandwidth limitations, the weight coefficients of which can be updated by using either the constant modulus algorithm (CMA) or a least mean square algorithm. In another study, validation results of a proof-of-concept DSP-free coherent transceiver for DCIs that uses dual polarization-16 quadrature amplitude modulation (DP-16QAM) format was reported [14]. Recently, an analog coherent engine, working up to 400 Gb/s dissipating 2 W of power, that uses ASP followed by a feed-forward equalizer filter to improve signal quality for 15 m SMF was demonstrated [9].

Studies on low-power analog coherent optics, based on optical phase-locked loop (OPLL), which work for very short distances due to the choice of low dispersion, but high attenuation O-band were also reported [15, 6]. Another work demonstrates a 40 Gb/s OPLL based analog coherent binary phase-shift keying receiver that uses the integration of electronic and photonic integrated circuits (ICs) to eliminate the usage of DSP for carrier offset removal [16]. Recently, a technique to achieve carrier phase synchronization using ASP based IC, phase modulator, and tunable lasers was demonstrated [18, 19]. Receivers in [16, 18] use OPLL for phase and frequency error correction to achieve significant power savings by removing DSP completely.

From the literature, it can be summarized that miniaturized analog coherent transceiver using electronic and photonic integration is a solution for the power dissipation-size-cost problem in the future DCIs. The block diagram of such a transceiver is given in Fig. 1. In a coherent transceiver, a major portion of the power is consumed by the receiver electronics which can be reduced if the main signal processing operations–equalization, carrier phase recovery and compensation (CPRC), and clock and data recovery (CDR) are carried out using ASP as shown in the figure. In the receiver side, an equalizer is used to mitigate the effects of channel dispersion. A CPRC is used to compensate for the phase and frequency mismatches between the transmitter and receiver lasers, and a CDR is used for clock recovery from the received signals.

Equalizer being the major power dissipating block in coherent optical receivers [20], we implemented an all-analog equalizer for a proof-of-concept validation of the ASP based transceiver. It can also be seen from the literature that analog domain processing is an attractive choice for low-power equalization in various types of high-speed links [21, 22, 23, 24, 25, 26, 27, 28, 29]. Specifically for optical links, a CMOS receiver with a continuous-time linear equalizer for 30 Gb/s links was reported in [26] and a monolithic optoelectronic IC designed in a 130 nm CMOS process that uses analog domain slope detection based adaptive equalizer was shown in [29] for links with a carrier of 850 nm wavelength. As a major milestone in this area, the first all-analog adaptive equalizer for DP-QPSK links was demonstrated in our previous work [12]. In this present work, we report the proof-of-concept demonstration of the equalizer operating at a rate as high as 40 Gb/s. We also present the detailed architecture of the equalizer and discuss the practical constraints and future directions of the ASP approach.

II System Overview

The optical-to-electrical (O/E) front-end of a DP-QPSK receiver gives out four electrical signals corresponding to the in-phase (I) and quadrature-phase (Q) components of the X and Y polarizations. These signals will not be independent of each other due to dispersion, polarization rotation, and polarization-dependent loss. Hence, a $4\times 4$ multi-dimensional equalizer needs to be used to process all the signals jointly. The equalizer should adaptively mitigate the dispersion effects of the fiber, which is a time-varying phenomenon. To adapt the equalizer weight coefficients, the CMA algorithm [30] is used, which is one of the simplest blind equalization algorithms that can be used with DP-QPSK signals.

Fig. 2(a) shows the architecture of the equalizer that uses the CMA algorithm to adapt the weight coefficients. The equalizer has a feed-forward block and an error generator. It has inputs $x$ and $y$ and outputs $x_{eq}$ and $y_{eq}$ which are complex signals corresponding to the X and Y polarizations, respectively. The feed-forward block has four transversal filters with coefficients $\bm{h}_{xx}$, $\bm{h}_{xy}$, $\bm{h}_{yx}$, and $\bm{h}_{yy}$ which are arranged as a butterfly structure. This structure generates equalized output signals, $x_{eq}$ and $y_{eq}$ from the inputs, and the CMA error signals $\varepsilon_{x}$ and $\varepsilon_{y}$, which are calculated in the error generator. The outputs of the equalizer are given by [11]

[TABLE]

where $\bm{x}$ and $\bm{y}$ are vectors containing delayed input signals. The update equations of the equalizer weight are given by [11]

[TABLE]

[TABLE]

[TABLE]

[TABLE]

where $\beta$ is a gain constant, $x=x_{I}+jx_{Q}$ and $y=y_{I}+jy_{Q}$ are the X and Y polarization input signals of the equalizer, $x_{eq}=x_{eq,I}+jx_{eq,Q}$ and $y_{eq}=y_{eq,I}+jy_{eq,Q}$ are the equalizer outputs in the corresponding polarizations, $\tau_{d}$ is the tap delay, and $0\leqslant k\leqslant L$, where $L$ is the total number of delay cells in each transversal filter. The CMA algorithm is known to converge for any positive value of the gain constant $\beta$ [31].

III Implementation Details

A fractionally spaced two-tap continuous-time CMA equalizer for 100 Gb/s DP-QPSK links is designed and fabricated using 130 nm SiGe BiCMOS technology from ST Microelectronics as a proof-of-concept. Fig. 2(b) shows a detailed block diagram of the prototype equalizer, which consists of linear transversal filters, error generators, and weight-update modules. The figure is a block-level translation of the system described by (1)-(5) with minor modifications to take care of the circuit level issues discussed in the following sub-section.

III-A Issues of Delay Mismatch and Signal Swing

Path delay is an inherent problem associated with any circuit which gets worse as the number of circuit blocks in the path is increased. This problem becomes crucial if the circuit has multiple parallel paths. Signal delays through the parallel paths are to be made equal over the desired frequency range. It is evident from (2)-(5) that there are parallel paths in the equalizer. Signals through the parallel paths get multiplied down the signal path. In such cases, delay cells are inserted in the paths that have lower group delays. In Fig. 2(b) delay cells $\tau_{c}$ are inserted to cancel the delay mismatch in the forward paths and $\tau_{e}$ are inserted to cancel the delay mismatch in the error generators. Equations (2)-(5) assume a normalized single ended signal magnitude which is taken as 100 mV in the circuit. Gains of all the building blocks are scaled according to this signal level. In Fig. 2(b) the expected amplitude is represented by $A$, which is 100 mV for a single-ended signal. Taking these into consideration, (2) can be modified as $h_{xx,k}(t)=\beta\int_{0}^{t}x_{eq}(\tau-\tau_{e})[A^{2}-|x_{eq}(\tau)|^{2}]x(\tau-k\tau_{d}-\tau_{c})d\tau.$ Equations (3)-(5) can also be modified in a similar way. It can be concluded from Fig. 2(b) that the main operations in the equalizer are delay, multiplication, addition, and integration. The following sub-section briefly describes design details of basic building blocks of the equalizer.

III-B Basic Building Blocks of the Equalizer

Building blocks of the equalizer are designed, integrated, and simulated in Cadence Virtuoso analog design environment. All integrated circuits, be it DSP or ASP based, are prone to device mismatches, offset issues etc. These issues are taken care of during the design phase by doing Monte Carlo analysis which is a statistical technique used in circuit simulation to account for tolerance issues in the circuit components using Gaussian random numbers. All these analyses are performed at the block level design, various levels of integration, and the overall equalizer. Responses of the building blocks presented in this paper are results of post-layout Monte Carlo simulations with 200 runs at 27°C with 50 fF parasitic capacitance at each output node. The simulations also include mismatches among circuit components, which is an important parameter when the system has differential circuits, and effects of process variations on device parameters such as the small signal current gain of BJTs and the threshold voltage of MOSFETs. Since the equalizer is adaptive, not all variations may be critical. These issues can also be handled well by using calibration techniques similar to the ones used in ADCs.

III-B1 Delay Cell

An active delay cell is chosen over a passive delay cell to save chip area and hence, for the ease of routing. The delay cell is implemented by cascading several degenerated common emitter (CE) stages followed by a common collector (CC) buffer to drive a large capacitive load. A circuit schematic of the delay cell is shown in Fig. 3(a). The group delay of the cell $\tau_{d}$ with five cascaded CE stages is shown in Fig. 3(b). The delay cell, with an area of $\sim$95 \mathrm{\SIUnitSymbolMicro m}$$\times50 $\mathrm{\SIUnitSymbolMicro m}$, has a DC gain of −1.4 dB, and a bandwidth of 20.7 GHz. This cell provides a group delay of 24.3 ps with a 10% delay-bandwidth of 22.1 GHz. The delay cells $\tau_{c}$ and $\tau_{e}$ are implemented similarly by varying the number of CE stages as per the delay needed. The values of $\tau_{c}$ and $\tau_{e}$ are determined by doing AC analysis based group delay measurement and transient analysis in the Cadence Virtuoso analog design environment.

III-B2 Multiplier

The multiplication operation is realized using the Gilbert cell topology [32]. Fig. 4(a) shows the schematic of the multiplier. The circuit has degeneration resistors for both the inputs to improve the linearity. The designed multiplier has a DC gain of 7.4 dB and a bandwidth of 20.2 GHz from I1 when I2 is 200 mV, and a DC gain of 6.02 dB and a bandwidth of 17.9 GHz from I2 when I1 is 200 mV. Due to the lower bandwidth of I2 low-speed signals such as filter weight coefficients are applied to this input. DC transfer characteristics of the multiplier is shown in Fig. 4(b). It can be observed that the maximum deviation from the linear region is only 10% in the signal swing of concern. A single multiplier occupies an area of $\sim$40 \mathrm{\SIUnitSymbolMicro m}$$\times45 $\mathrm{\SIUnitSymbolMicro m}$. A complex multiplier is implemented by connecting four such Gilbert cells, and a squaring circuit by giving the same signals to both the inputs of a Gilbert cell.

III-B3 Adder

The addition operation is performed in the current domain by adding two current signals onto a common resistor. This technique is used in blocks such as complex multiplier where routing is minimal. When an additional gain is required, two degenerated CE sections are used with common load resistors, as shown in Fig. 5. This adder has 12.3 dB DC gain and 18.4 GHz bandwidth. For the convenient placement in the equalizer layout, the adder is designed as half circuits, each of which has an area of $\sim$20 \mathrm{\SIUnitSymbolMicro m}$$\times40 $\mathrm{\SIUnitSymbolMicro m}$.

III-B4 Integrator

The settling behavior and steady-state error performance of the equalizer are primarily decided by the DC gain and cut-off frequency of the integrator, which makes it a critical building block. A folded BiCMOS amplifier topology with a large capacitive load is chosen to get a very high DC gain without compromising the pole locations. A circuit schematic of the integrator is shown in Fig. 6(a). The high gain amplifier of the integrator is a modified version of the basic folded cascode amplifier discussed in [32] and the G${}_{\text{m}}$ stage of the amplifier is designed with bipolar transistors as suggested in [33]. To obtain a very low-frequency pole without affecting the high gain, the output resistance of the circuit has to be maximized. Hence, the cascode section of the amplifier is biased at a low current. The amplifier gain is given by $|A_{V}|\approx g_{m,Q_{P1}}\{[(g_{m,P_{3}}+g_{mb,P_{3}})r_{o,P_{3}}(r_{o,Q_{P1}}||r_{o,P_{1}})||[(g_{m,N_{3}}+g_{mb,N_{3}})r_{o,N_{1}}r_{o,N_{3}}]\},$ the output resistance is given by $R_{O}\approx[(g_{m,P_{3}}+g_{mb,P_{3}})r_{o,P_{3}}(r_{o,Q_{P1}}||r_{o,P_{1}})]||[(g_{m,N_{3}}+g_{mb,N_{3}})r_{o,N_{1}}r_{o,N_{3}}],$ and the cut-off frequency is given by $f_{3\,dB}\approx{1}/{2\pi R_{O}C_{L}}$ [32]. The integrator shown in Fig. 6(a) has a common-mode feedback (CMFB) structure consisting of transistors N5-N9 and the dummy transistors Q${}_{\text{P}2}$ and Q${}_{\text{N}2}$. A detailed design of the CMFB can be found in [32]. The integrator has an area of $\sim$120 \mathrm{\SIUnitSymbolMicro m}$$\times160 $\mathrm{\SIUnitSymbolMicro m}$ and a DC gain of 103.9 dB with a bandwidth of 56.2 Hz.

To initialize the weight coefficients, a reset circuit shown in Fig. 6(b) is connected to the output of the integrator. An enable signal, EN1 is applied at the startup of the equalizer operation which turns switches N3 and N4 on. The enable signal EN2, a delayed version of EN1, is used to avoid any unwanted discharge of C${}_{\text{L}}$. Different combinations of R1 to R4 are chosen so as to initialize the weight coefficients at the integrator output nodes. When a global reset signal is asserted the equalizer tap coefficients are reset to the values $\bm{h}_{xx}=[1+j~{}~{}0]^{T}$, $\bm{h}_{xy}=[0~{}~{}0]^{T}$, $\bm{h}_{yx}=[0~{}~{}0]^{T}$, and $\bm{h}_{yy}=[1+j~{}~{}0]^{T}$.

III-B5 Output Buffer

Output nodes of the equalizer are designed to drive high-speed transmission lines. To match impedance at the output nodes CE buffers are used, a schematic of which is shown in Fig. 7(a). The parallel combination 2R${}_{\text{C}}||$R${}_{\text{L}}$ helps to match the impedance without decreasing the value of R${}_{\text{C}}$. This configuration also helps to achieve different AC and DC output resistances while maintaining the transistors in the active region of operation. The buffer has 4.9 dB DC gain, 37.8 GHz bandwidth, and occupies $\sim$44 \mathrm{\SIUnitSymbolMicro m}$$\times46 $\mathrm{\SIUnitSymbolMicro m}$ area. The output of the buffer has a differential output resistance of 99.7 $\Omega$ as shown in Fig. 7(b).

III-B6 Other Building Blocks

Level shifters are used to shift common-modes up or down at various nodes, and AC coupling is used wherever level shifting is not possible. All bias currents are mirrored from a single source which is supplied from outside. To match the impedance of high-speed inputs, a circuit shown in Fig. 8(a) is used. This circuit provides 100 $\Omega$ differential input resistance, and the desired common mode to the input signals. There is also an electro-static discharge (ESD) protection circuit made up of ESD diodes. Simulations show an $S_{11}$ parameter, which is better than −10 dB in the frequency band of concern, as shown in Fig. 8(b).

III-C The Equalizer IC

A micrograph of the prototype equalizer is shown in Fig. 2(c). The IC has 50 pads of which 28 are meant for high-speed differential signals which are arranged in a ground-signal-signal-ground-signal-signal-ground pattern. Rest of the pads are used for reset signal, bias current, amplitude control signals, and supply voltage and ground. The equalizer occupies $\sim$1.4 mm$\times$1.35 mm chip area and consumes 2.5 W. The power consumption remains the same for data rates of up to 100 Gb/s since the chip uses a constant current biasing.

IV Results and Discussion

The CMA equalizer is designed to operate at 100 Gb/s. However, high-speed assembly/packaging constraints limited testability of the chip to 40 Gb/s data rate.

IV-A Measurement Results at 40 Gb/s Data Rate

Fig. 9 shows a block diagram of the experimental setup with a 40 Gb/s DP-QPSK system. In this setup, an external cavity laser of 1550 nm wavelength is used as the carrier source at the transmitter. A 50:50 power splitter (PS) divides the laser output into two parts–one of which gets modulated at the transmitter and the other is used as a local oscillator (LO) at the receiver. Two independent 10 Gb/s data streams are generated using a 10 Gb/s pseudo-random binary sequence generator which is clocked by a 10 GHz source. The two data streams are amplified to drive the nested Mach-Zehnder modulator (MZM). The MZM gives out a 20 Gb/s QPSK modulated carrier which is split into X and Y polarizations using a polarization beam splitter (PBS). The X output of the PBS is directly connected to the X input of a polarization beam combiner (PBC), whereas the Y output is delayed using a 2 m-long polarization maintaining fiber before connecting to the Y input of the PBC. This optical delay is used to de-correlate the X and Y QPSK signals. The MZM-PBS-optical delay-PBC combination emulates a DP-QPSK modulator which gives out a 40 Gb/s DP-QPSK modulated carrier to the channel.

At the receiver side, the signal from the channel, S and the LO are fed to the inputs of an integrated coherent optical receiver front-end. The required power level of the LO is maintained using a variable optical attenuator (VOA), which is connected just before the receiver front-end. The receiver front-end consists of PBSs, 90°optical hybrids, balanced photo-diodes, trans-impedance amplifiers, and automatic gain control in the mentioned order. This module maintains a differential signal level of 400 mVpp on all four inputs of the equalizer IC which is wire-bonded to a printed circuit board (PCB). The PCB shown in Fig. 10 is fabricated using RT duriod/6010LM laminate, more details of which can be found in [34]. The PCB has four pairs of input transmission lines as well as output transmission lines which end on SMA connectors mounted along the periphery of the PCB. The outputs of the equalizer are stored using a 21 GHz real-time oscilloscope for further processing with a behavioral model of a CPRC. Fig. 11 shows the block diagram of the behavioral CPRC that consists of a single sideband mixer, phase detector, loop filter, and quadrature-phase voltage controlled oscillator. Further details of the CPRC can be found in [11].

The error vector magnitude (EVM) of the output signal is calculated by sampling the CPRC outputs at the maximum eye-opening point. The EVM is calculated as

[TABLE]

where $I_{k}$ and $Q_{k}$, respectively are the I and Q components of the $k^{\text{th}}$ received symbol, $\widehat{I_{k}}$ and $\widehat{Q_{k}}$, respectively are the expected I and Q components of the $k^{\text{th}}$ received symbol, $A$ is the expected radius of the constellation points, and $N$ is the total number of received symbols.

Performance of the equalizer is characterized using the 40 Gb/s system for different link lengths. Fig. 12 shows the eye-diagrams obtained at various stages of the experimental setup with a back-to-back optical link. The eye-diagram shown in Fig. 12(a) is that of the transmitted signal with 24% EVM. No pre-equalization or pre-compensation are performed to nullify the effects of components non-idealities, which resulted in a poor transmitter EVM. Fig. 12(b) shows the received signal eye-diagram, which is distorted due to the system non-idealities. Fig. 12(c) shows the equalizer chip’s output eye-diagram and Fig. 12(d) shows the behavioral CPRC’s output eye-diagram with 28% EVM which corresponds to an estimated bit error rate (BER) of $1.8\times 10^{-4}$. The BER is estimated from the EVM as

[TABLE]

where $P$ is number of levels per dimension and $M$ is the number of symbols on the I-Q plane [35].

X polarization constellations at various stages of the system are shown in Fig. 13 with results of a back-to-back link in the top row, a 5 km link in the middle row, and a 10 km link in the bottom row. The received optical powers are −7.2 dBm, −10.4 dBm, and −11.6 dBm, respectively and the minimum requirement of the coherent receiver front-end is −20 dBm. Since the same laser is used at the transmitter and receiver, there is only a minimal phase offset between the received signal and LO at the receiver in the back-to-back link. Under this condition, the equalizer recovers four constellation points, but with a slight rotation due to the phase insensitivity of the CMA algorithm. However, in 5 km and 10 km links, a large optical path difference between the signal and LO results in a frequency offset which is evident from the equalized constellation diagrams, which appear as rings on the I-Q plane. Post-processing carried out with the behavioral CPRC results in the constellations shown in Fig. 13(c) with an EVM of 28% in the back-to-back, 32% in the 5 km, and 33% in the 10 km links. The corresponding estimated pre-forward error correction (pre-FEC) BERs are $1.8\times 10^{-4}$, $8.9\times 10^{-4}$, and $1.2\times 10^{-3}$, respectively, which are well below the hard-decision FEC limit. The intensity noise in the output constellation can be attributed to the frequency dependent S-parameters of the transmission lines of the test PCB [34].

IV-B Post Layout Simulation Results at 100 Gb/s Data Rate

The small pad-pitch and the large pin count of the chip limited the board assembly and packaging options, hence the experimental validation of the equalizer at the designed data rate is not performed. Also, the small pad pitch of the IC limited the possibilities of an optimal direct die attach and a very well matched on-PCB transmission lines. Apart from these, issues owing to the bandwidth limitation due to bond-wire inductance, transmission lines, and SMA connectors, functionality of the equalizer at 100 Gb/s is verified through post-layout simulations. A 100 Gb/s transmission system is modeled in VPItransmissionMaker from which the received signals after the O/E conversion are exported for post-layout circuit simulation. Fig. 14 shows the results of a post-layout simulation carried out in typical-typical corner with the data from a simulation model of an optical link with a 5 km SMF channel. Fig. 14(a) shows the eye-diagram of the transmitted data with an EVM of 1%, which becomes distorted when it reaches the receiver side, as shown in Fig. 14(b). Fig. 14(c) is the eye-diagram of the equalizer output and Fig. 14(d) is the output of a behavioral CPRC with an EVM of 27.8%.

IV-C Challenges and Future Directions

Due to packaging limitations, the measured performance of the equalizer IC is sub-optimal and the IC could not be tested beyond 40 Gb/s data rate. A flip-chip-on-board assembly would have resulted in a better performance from the IC, but such a setup was not feasible as the pad-pitch is very small. A fine-tuned optical system employing pulse shaping at the transmitter side to help with effective bandwidth utilization and a PCB with well-matched transmission lines are also expected to improve the experimental setup. The major limiting factor of all-analog processing would be the bandwidth reduction due to the cascading effect. This would restrict the maximum amount of dispersion to be corrected since a larger amount of dispersion requires a larger number of cascaded taps in the equalizer. However, usage of on-chip transmission lines and a combination of active and passive delay lines would help to increase the number of taps. Also, optimizing the delay cell can increase the number of cascaded stages in the delay line [36, 37]. It is seen that the delay cells contribute significantly to the overall power consumption of the IC. However, by optimizing the delay cell in the same node a significant overall power reduction is also reported [38].

Usage of a lower technology node will help to reduce the power consumption, which may be inferred from [39, 40, 41, 42]. Implementation using FinFET technology is also expected to reduce power consumption and improve performance because of a lower supply voltage and a higher transit frequency ($f_{T}$). For example, an ADC, which is an analog circuit, in 14 nm FinFET technology [41] shows a 30X improvement in energy efficiency (mW/bit/GHz) over an ADC in 130 nm BiCMOS [42]. If implemented using FinFET Technologies, we can expect the equalizer’s energy efficiency (mW/Gb/s) also to improve by a similar factor.

The equalizer presented in this paper is meant for DP-QPSK format. By using the analog blocks designed for the equalizer it is possible to implement other adaptive algorithms too. For example, a 16QAM equalizer that uses a radius directed equalizer algorithm is presented in [43]. Other critical blocks at the receiver side are also being investigated successfully for 16QAM. For instance, an analog domain Costas loop-based CPRC IC for QPSK and 16QAM formats is demonstrated quite recently in [18, 19]. These advances give a clear indication that the ASP technique is scalable and is a good solution for the power consumption-size-cost problem of the DCI transceivers. A comprehensive comparative study on DSP and ASP techniques is reported in [44]. It shows an energy consumption of 65.53 mW/Gb/s by an ASP based coherent receiver while that of 210.46 mW/Gb/s by a DSP based coherent receiver at 200 Gb/s operation emphasizing a $\sim$3X reduction in energy consumption per bit using ASP.

V Conclusion

The detailed architecture and demonstration of the first all-analog equalizer for DP-QPSK links are presented in this paper. A two-tap proof-of-concept prototype of the equalizer, that uses the CMA algorithm to update weight coefficients, is implemented in a 130 nm BiCMOS technology. Measurement results of the equalizer IC obtained with a 40 Gb/s, back-to-back link show an EVM that is very close to the transmitter EVM, which clearly indicates that the IC is not deteriorating signal quality and not introducing significant noise and non-linearity. Measurement results obtained with a 40 Gb/s, 10 km SMF link that uses 1550 nm wavelength carrier show that the equalizer can easily replace the existing ADC+DSP based equalizers for short-reach, high-capacity DCIs. 100 Gb/s post-layout simulation results of the equalizer IC indicate that its architecture can be used to enhance the capacity of optical links. The same architecture can be used for links with longer channel lengths if the carrier wavelength is 1310 nm or for links that use dispersion-shifted fibers.