Reconfigurable multiplier architecture based on memristor-cmos with higher flexibility

TL;DR

This paper presents a memristor-CMOS reconfigurable multiplier that offers flexible bit-width multiplication, reducing area and adapting to various algorithms in digital signal processing systems.

Contribution

It introduces a novel memristor-CMOS hybrid architecture for a reconfigurable multiplier with adjustable bit-width, enhancing flexibility and efficiency over fixed multipliers.

Findings

Reduces area occupation compared to traditional multipliers

Provides flexible bit-width multiplication for diverse algorithms

Demonstrates performance using memristor SPICE model and 180-nm CMOS process

Abstract

Multiplication is an indispensable operation in most of digital signal processing systems. Recently, many systems need to execute different types of algorithms on a multiplier. Therefore, it needs complicated computation and large area occupation. In this regard a fixed multiplier is inefficient and the development of a reconfigurable multiplier becomes increasingly important. The advent of memristor-CMOS hybrid circuits provides an opportunity for reducing area occupation. This paper introduces memristor-CMOS based reconfigurable multiplier which provides flexible multiplication according to various bit-width. Performance of the proposed multiplier is estimated with some applications and comparison with conventional multipliers, using memristor SPICE model and proprietary 180-nm CMOS process.