# PPAC: A Versatile In-Memory Accelerator for Matrix-Vector-Product-Like Operations

## TL;DR

PPAC is a versatile in-memory accelerator supporting various matrix-vector operations, improving throughput and energy efficiency for multiple applications like neural networks, hashing, cryptography, and error correction.

## Contribution

It introduces PPAC, a fully-digital, CMOS-compatible in-memory accelerator capable of handling diverse MVP-like operations, unlike existing specialized or limited PIM architectures.

## Key findings

- Post-layout 28nm CMOS implementation results demonstrate competitive throughput.
- PPAC outperforms recent digital and mixed-signal PIM accelerators in efficiency.
- Supports a wide range of applications, simplifying development.

## Abstract

Processing in memory (PIM) moves computation into memories with the goal of improving throughput and energy-efficiency compared to traditional von Neumann-based architectures. Most existing PIM architectures are either general-purpose but only support atomistic operations, or are specialized to accelerate a single task. We propose the Parallel Processor in Associative Content-addressable memory (PPAC), a novel in-memory accelerator that supports a range of matrix-vector-product (MVP)-like operations that find use in traditional and emerging applications. PPAC is, for example, able to accelerate low-precision neural networks, exact/approximate hash lookups, cryptography, and forward error correction. The fully-digital nature of PPAC enables its implementation with standard-cell-based CMOS, which facilitates automated design and portability among technology nodes. To demonstrate the efficacy of PPAC, we provide post-layout implementation results in 28nm CMOS for different array sizes. A comparison with recent digital and mixed-signal PIM accelerators reveals that PPAC is competitive in terms of throughput and energy-efficiency, while accelerating a wide range of applications and simplifying development.