Analog content addressable memories with memristors

TL;DR

This paper introduces an analog content-addressable-memory design using memristors that leverages their conductance tunability to reduce area and power consumption, enabling faster and more versatile pattern matching applications.

Contribution

It presents a novel analog CAM architecture with memristors, overcoming limitations of binary/ternary schemes and expanding application potential.

Findings

Reduces area and power consumption compared to traditional designs

Demonstrates feasibility through experiments and simulations

Enables new computing applications with analog data storage

Abstract

A content-addressable-memory compares an input search word against all rows of stored words in an array in a highly parallel manner. While supplying a very powerful functionality for many applications in pattern matching and search, it suffers from large area, cost and power consumption, limiting its use. Past improvements have been realized by using memristors to replace the static-random-access-memory cell in conventional designs, but employ similar schemes based only on binary or ternary states for storage and search. We propose a new analog content-addressable-memory concept and circuit to overcome these limitations by utilizing the analog conductance tunability of memristors. Our analog content-addressable-memory stores data within the programmable conductance and can take as input either analog or digital search values. Experimental demonstrations, scaled simulations and analysis show that our analog content-addressable-memory can reduce area and power consumption, which enables the acceleration of existing applications, but also new computing application areas.

Figures

Tables

Table 1. Table 1: Write operation of the analog CAM cell

Operation	SL_hi	SL_lo	DL1	DL2
Set M1	Vset	0	Vg,set	0
Reset M1	0	Vreset	VDD	0
Set M2	Vset	0	0	Vg,set
Reset M2	0	Vreset	0	VDD
Read M1	Vread	0	VDD	0
Read M2	Vread	0	0	VDD

Table 2. Table 2: Energy break down during searches in a 86 × 12 86 12 86\times 12 array

Supply	Energy/search	Energy/search/cell
ML precharging	102.9 fJ	0.10 fJ
SLhi driver	298.5 fJ	0.29 fJ
Others	86.4 fJ	0.08 fJ
DAC	52.1 fJ	0.05 fJ
Total	539.9 fJ	0.52 fJ

Equations

$$G_{\text{M1}}\cdot (V_{\text{SLhi}}/V_{\text{TH,ML}}-1)/\beta +V_{\text{TH}}\le V_{\text{DL}}\le G_{\text{M2}}\cdot (V_{\text{SLhi}}/V_{\text{TH,inv}}-1)/\beta +V_{\text{TH}}$$

$$G_{\text{T, ON}}>\left[\left(\beta -1\right)N+1\right]\cdot G_{\text{T, OFF}}$$

$$G_{\text{T}}=f(V_{\text{DL}})<G_{\text{th}}-(N-1)\cdot G_{\text{T, OFF}}$$

Full text

A content-addressable-memory compares an input search word against all rows of stored words in an array in a highly parallel manner. While supplying a very powerful functionality for many applications in pattern matching and search, it suffers from large area, cost and power consumption, limiting its use. Past improvements have been realized by using memristors to replace the static-random-access-memory cell in conventional designs, but employ similar schemes based only on binary or ternary states for storage and search. We propose a new analog content-addressable-memory concept and circuit to overcome these limitations by utilizing the analog conductance tunability of memristors. Our analog content-addressable-memory stores data within the programmable conductance and can take as input either analog or digital search values. Experimental demonstrations, scaled simulations and analysis show that our analog content-addressable-memory can reduce area and power consumption, which enables the acceleration of existing applications, but also new computing application areas.

Introduction

To increase power efficiency and cost performance, there is growing interest in computing architectures that allow for in-memory processing[1] in order to reduce data movement and address the memory wall. In this vein, recent work has shown the promise of using non-volatile memory devices, or memristors, for accelerating matrix multiplication directly in memory arrays, accelerating a range of applications such as machine learning[2, 3, 4, 5, 6], analog signal processing[7, 8], and scientific computing[9, 10, 11]. The performance improvements from this approach originate from two principles. First, computation is performed where the data is stored, removing the expensive power and latency costs of data movement between separate computing and memory units in a von-Neumann machine. Second, computation is performed in the analog domain, which provides exponential efficiency gains over digital, particularly at lower precision requirements. Each device performs analog computations that would otherwise require multiple digital elements. Despite the great promise of this approach, demonstrations have thus far been limited to the acceleration of matrix multiplication via crossbars.

Meanwhile, in-memory computational approaches in the digital domain have been extensively explored over the years[12]. While many proposed circuit typologies have not been implemented in commercial systems, content addressable memory (CAM) and the related ternary CAM (TCAM) have stood as a notable exception[13, 14]. CAM/TCAM circuits natively perform a matching operation between an input data word (search key) and a stored set of data patterns in the CAM/TCAM array. The operation is highly parallel and another example of an in-memory operation, leading to extremely high throughput compare operations at low latency, and therefore commercial success in applications such as network routing[15, 16], real-time network traffic monitoring[17], and access control lists (ACL)[18]. While powerful, CAM performance benefits come at the cost of large power and low memory density, limiting modern usage to high cost niche areas that demand high performance. Recent work has shown that utilizing non-volatile memristors (or resistive memory devices) in TCAM circuits reduces area and power[19, 20, 21, 22, 23, 24, 25, 26, 27] and provides the flexibility to accelerate powerful finite state machines, particularly for Regular Expression matching used in Network Intrusion Detection Systems[23, 28]. However, nearly all memristor-based CAM designs utilize schemes similar to conventional static random-access-memory (SRAM) designs where the memristor only encodes binary states. The highly tunable analog conductance in memristor devices, with many stable intermediate states are not leveraged[29]. An analog CAM design was proposed more than a decade ago that matches an input voltage with precise values stored in analog storage cells[30], but has not been implemented likely due to practical concerns of high power and area as it requires large numbers of active comparators and inefficient array implementations.

Here, we propose a memristor-based analog CAM that significantly increases data density and reduces operational energy and area for these in-memory processing circuits. Our analog CAM design stores a range of values in each cell using the tunable conductance of memristive devices, and compares an analog input with this stored range to determine a match or mismatch. The concept has been validated with proof-of-concept experiments, as well as simulations to establish performance and scalability. When used to store narrow ranges as discrete levels, our analog CAM can be a direct replacement of digital CAMs while providing higher memory densities and smaller power consumption. This may enable the use of CAMs for more generic scenarios[31, 32, 33, 34] such as for associative computing that otherwise struggle with the limited memory densities and high power consumption of conventional CAMs. More importantly, our analog CAM can store wide intervals of continuous levels, thereby enabling novel search and matching functionality in the analog domain. The analog CAM cell presented here can also be searched with analog input signals, enabling the processing of analog sensor data without the need for an analog-to-digital conversion step.

Results

0.1 6-transistors 2-memristors analog content addressable memory

The proposed analog CAM concept is illustrated in \Mfigure1, where analog voltage values are input to the analog CAM to be searched against the analog ranges encoded by multilevel conductances in the memristors. This is distinct from all previously reported CAMs (SRAM or memristor-based), where only digital signals are searched and stored (\Mfigure1a). Similar to a digital CAM, the ‘match’ signal for each row is generated on the matchline (ML) only when all the inputs for every column match the data stored in that row’s memory. In contrast to digital CAMs, each analog CAM cell can match a range of analog input voltages (\Mfigure1b), instead of a digital value. The analog CAM can be configured to match a narrow range of discrete values, and therefore one analog CAM cell is a direct functional replacement for multiple digital CAM cells. In addition, similar to storing a ‘wild card’ or ‘X’ in the TCAM, the proposed analog CAM can also store a range of continuous values, which would otherwise be difficult to implement with digital CAMs/TCAMs, but (as described later) is beneficial in internet packet (IP) routing, and more novel applications in decision trees, associative computing[35, 34] and probabilistic computing.

To realize the proposed analog CAM concept, we have designed an analog CAM cell circuit where each cell is composed of six transistors and two memristors (6T2M) (\Mfigure2a). The analog input search data is mapped to voltage amplitudes VDL applied along datalines (DL), and the stored analog range is configured by the programmed conductances of the two memristors of the cell (\Mfigure2b). Similar to existing CAM circuit implementations, the search operation starts by precharging each row’s ML to a high logic level, and the MLs stay high (match) only when all of the attached CAM cells of a row match the corresponding input, otherwise discharging and leading to a low logic level (mismatch) on the ML. In the 6T2M design, the ML is connected to pull-down transistors (T1, T2), and is kept high for a ‘match’ result when the gate voltage of the pull-down transistors is smaller than the threshold voltage, keeping the transistor channel in a high resistance state.

Each analog CAM cell stores an upper and lower bound for matching against the input search value. These bounds are encoded by two voltage divider sub-circuits which determine the gate voltages of two pull-down transistors connected to the ML. As shown in \Mfigure2c, the voltage divider sub-circuit consists of a transistor and series connected memristor, which generates the gate voltage (G1) of the pull-down transistor (T1) in the 6T2M analog CAM circuit to embody analog CAM cell’s lower bound match threshold. When VDL is larger than a certain threshold voltage, the transistor is highly conductive and thus the search voltage between SL_hi and SL_lo (typically at GND) will mainly drop across the M1 memristor, resulting in a small voltage on G1 that does not turn on the pull-down transistor and yields a match result. The lower bound of the input voltage VDL that yields a match is configured by tuning the memristor conductance in the voltage divider. The upper bound of the search range is configured similarly with an independent voltage divider using M2 and an inverter to control the gate voltage (G2) of the second pull-down transistor (T2) (\Mfigure2b). This concept is shown by the simulation of the voltage on G1 and G2 depending on VDL with different M1 and M2 memristor conductances (\Mfigure2c, d). As a result, the cell keeps ML high only when VDL is within a certain range as defined by the M1 and M2 conductances. As several cells are connected on the same ML in a row, just as in digital CAMs, a row ML outputs ‘high’ only when each cell in the row matches.

0.2 Simulations and experiments

To validate our circuit design and further investigate the memristor-based analog CAM concept, we (1) conducted extensive simulations of individual analog CAM cells and CAM arrays and (2) experimentally measured analog CAM circuit operation in a taped-out silicon test chip. The circuit simulations shown here utilize 16nm design rules to enable projected performance comparisons against current CMOS-based solutions, and our silicon tape-out utilized a 180nm technology node to provide voltage and current overheads and accelerate design to fabrication time.

We first validated the operation of the individual memristor analog CAM cell circuit with circuit simulations (see Methods for details) based on a layout using commercial $16\text{\,}\mathrm{nm}$ design rules. The memristor conductance tuning in an analog CAM array is similar to the ‘write’ operation in a 1T1M array and described in the \SInote3, and \SIfigure6, with the parameter summarized in \SItable1. The current design prioritizes feasibility and demonstration of this new circuit concept and is not fully optimized for speed or power consumption.

The analog stored value was first configured in the CAM cell by setting the conductance of two memristors in one analog CAM cell to $40\text{\,}\mathrm{\SIUnitSymbolMicro S}$ and $80\text{\,}\mathrm{\SIUnitSymbolMicro S}$ and apply different $V_{\text{DL}}$ values to observe the changing $V_{\text{ML}}$ behavior during the search operation. From simulations we see that after the search is initiated (by pulling SL_hi high), $V_{\text{ML}}$ stays high (\Mfigure3b) when $V_{\text{DL}}$ is $0.4\text{\,}\mathrm{V}$, indicating a ‘match’, but is discharged low when $V_{\text{DL}}$ is either $0.3\text{\,}\mathrm{V}$ or $0.5\text{\,}\mathrm{V}$ for a ‘mismatch’. The operation’s timing diagram and voltage parameters are presented in \SIfigure7, from which one sees that the search result can be measured from the transient $V_{\text{ML}}$ at some time (e.g.$100\text{\,}\mathrm{ps}$) following the search when the voltage difference (i.e. sensing margin) between match and mismatch scenarios is large enough for a sense circuit. The simulated ML sensing output at $100\text{\,}\mathrm{ps}$ following the search operation for different $V_{\text{DL}}$ (\Mfigure3c) shows that this programmed memristor configuration corresponds to matching for $0.37\text{\,}\mathrm{V}$ $<V_{\text{DL}}<$ $0.42\text{\,}\mathrm{V}$. The lower bound (V_lo) and the upper bound (V_hi) of the analog CAM cell’s acceptable matching range can be configured independently by tuning the corresponding memristor conductance in the cell. Using the resulting mapping between the voltage bound and conductances (\Mfigure3d) as a guide, we configured analog CAM cells to match various voltage ranges (\Mfigure3e) or eight narrower ranges (\Mfigure3f) for representing 3-bit discrete voltage levels. CMOS process variation effects are studied with a layout-based simulation under different corner conditions, and results (in \SIfigure8) show that while different conditions slightly change the latency and search boundaries, we can still perform a calibration under those specific conditions to achieve the same bit accuracy as our search boundary is programmed with an iterative program-and-verify approach. Therefore, the proposed analog CAM cell implements the desired functionality and can be used to search for discrete levels (encoding at least 3-bits in a single cell) or for arbitrary analog voltage ranges to encode continuous values.

Next, we experimentally verified the proposed analog CAM operation in 6T2M analog CAM cells designed and fabricated at a 180 nm technology node on a silicon test chip (see Methods). Memristors of size 50\text{\,}\mathrm{nm}$$\times$$50\text{\,}\mathrm{nm} and based on Ta/\ceTaO_x were monolithically integrated in a Back End of the Line (BEOL) process with CMOS circuits on top of metal 6 and tungsten vias (\Mfigure4a). \Mfigure4b shows the top view image of the analog CAM array with integrated memristors. The integrated memristors have a wide $\sim 10^{3}$ range of conductance tunability (\Mfigure4c) and a programming voltage <$$1\text{\,}\mathrm{V} under direct-current (DC) sweeps (\Mfigure4d shows a typical switching curve, and \SIfigure9 shows a test chip under measurement), enabling us to validate the search operations experimentally. Given that the switching voltage of the memristor device exhibits a certain degree of variation, some devices may require a larger voltage to program than others (see \SIfigure10a). Therefore, it may impose challenges for a future technology node which supplies a voltage smaller than $1\text{\,}\mathrm{V}$. We programmed two analog cells in the same row to store different ranges using an iterative program-and-verify approach. We observe the match line (ML) pull-down current as we sweep the corresponding data line (DL), with the experimental configuration schematic in \SIfigure11a. As expected, the pull down current is low only when the applied data line voltage falls into the programmed range, indicating a match (\Mfigure4e), and the other cell attached to the same ML shows a different search range (\SIfigure11b,c). \Mfigure4f shows 1,000 repeated measurements without any observed disturb effects in the stored range (see also \SIfigure11d) and \SIfigure12 and 10 show the stability statistics of the analog conductance states of the memristors. These results suggest our analog CAM does not require static power to store a range table, nor frequent updates once programmed.

The relationship between an analog CAM cell’s stored range for a match and the programmed memristor conductances can be understood by the series connected transistor and memristor voltage divider (see \Mfigure2c, 2d). During a search operation, the serial transistors in the divider are working in the triode regime, as the voltage drop across the transistor channel is fairly small. Under this condition, $V_{\text{ML}}$ stays high when $V_{\text{DL}}$ follows \Mequation1, with bounds from the lower bound M1 voltage divider and the higher bound M2 voltage divider.

[TABLE]

where $V_{\text{TH}}$, $V_{\text{TH,ML}}$, $V_{\text{TH,inv}}$ are the threshold voltages of the transistor in the M1 voltage divider, the T1 pull-down transistor, and the inverter respectively. $\beta$ ($=\partial G_{\text{T}}/\partial V_{\text{DL}}$) is a constant coefficient in the transistor transfer function. $G_{\text{M1}}$ and $G_{\text{M2}}$ are the memristor conductances, which are linearly related to the accepted $V_{\text{DL}}$ for a match according to the above equation. This analysis is consistent with the results shown in \Mfigure3d when the transistor is working in the linear regime, but when the memristor conductance is very small (i.e. the transistor voltage drop is small) a numerical simulation is required to extract the precise relation. In practice, we use the simulated relation in \Mfigure3d to determine the programming target memristor conductance values from the desired stored analog value or range. Under this assumption, we scale up our simulations from single cells to large analog CAM arrays to predict performance.

0.3 Memristor analog content-addressable-memory arrays

While we have demonstrated single analog CAM cell operation in a small array, it is crucial to investigate whether large arrays can be operated without degradation to the desired search operation result. Using extracted parasitic parameters from the 16 nm layout, we constructed analog CAM arrays with arbitrary numbers of rows and columns (see Methods) to study how the analog CAM performs with increasing array size. \Mfigure5a shows the simulation configuration, where the two memristors in each of the analog CAM cells are programmed to $20\text{\,}\mathrm{\SIUnitSymbolMicro S}$ and $80\text{\,}\mathrm{\SIUnitSymbolMicro S}$ in order to accept $V_{\text{DL}}$ from $0.33\text{\,}\mathrm{V}$ to $0.43\text{\,}\mathrm{V}$. All DLs are biased to $0.4\text{\,}\mathrm{V}$, except for one column DL that is swept from $0.0\text{\,}\mathrm{V}$ to $1.0\text{\,}\mathrm{V}$ to observe how $V_{\text{ML}}$ changes. This single-bit mismatch is the worst-case scenario as it represents the situation where the mismatch $V_{\text{ML}}$ decay is the closest to the match $V_{\text{ML}}$ behavior. Since all cells with V_{\text{DL}}=$$0.4\text{\,}\mathrm{V} match, the $V_{\text{ML}}$ drop leading to a ‘mismatch’ is initiated by the cells in the column with the sweeping DL. Similar to a conventional CAM, ML discharging latency increases with the number of columns because of larger ML capacitances (\Mfigure5b). With increasing number of rows, on the other hand, the latency only changes 5% in our simulation for an array with 512 rows, suggesting our analog CAM supports the search for many entries in parallel.

As expected even with conventional CAMs, increasing the number of columns can also lead to a degradation of the $V_{\text{ML}}$ (\Mfigure5c) such that the acceptable search range is slightly changed. Our analysis shows that the degradation of $V_{\text{ML}}$ with increasing column number from the sub-threshold leakage current of the pull-down transistors (see \SInote3 for more details), and it can be improved with some emerging devices with extremely low leakage current and sharp transition, as we preliminary explored in \SInote3, \SIfigure13, \SIfigure14, and \SIfigure15. Nevertheless, the change in the accepted voltage range is within $0.02\text{\,}\mathrm{V}$ and is thus sufficient to separate more than 20 discrete levels between 0.2 V and 0.6 V for 4 bit searching capability in a 64-column analog CAM array. On the other hand, analog CAM arrays with two columns but an increasing number of rows show little change (\Mfigure5d) in $V_{\text{ML}}$ with additional rows (simulated up to 512 rows), demonstrating negligible row-wise interference.

0.4 Applications

The direct advantages of our proposed analog CAM are the improvements in energy and area over existing digital approaches. To demonstrate the potential scale of these improvements, we compared our analog CAM approach with the digital-equivalent for the usecase of classifying Internet protocol (IP) packets, which is a common commercial application for CAMs[13]. The ternary wildcard ‘X’ capability of TCAMs is frequently used to compress multiple table entries into fewer rows in the IP routing look-up table, owing to the fact that most classifying ranges are continuous. With our proposed analog CAM’s ability to store broad ranges, this look-up table can be further compressed. Analysis in the previous section suggested that one analog CAM cell is capable of searching 8-64 discrete levels, depending on the size of array and the specific implementation. Columns can therefore be combined as fewer cells are required to store the same amount of information. Additionally, by taking advantage of the range storage capability, fewer rows are required than in a digital CAM/TCAM representation. A real example is given in \SInote3 and \SIfigure16, which shows a 14x reduction in number of required cells from conventional TCAM to 16-level analog CAM cells, with further reductions possible with improved analog CAM cells. As an area improvement, we estimate an 18.8$\times$ reduction for our analog CAM $12.5\text{\,}{\mathrm{\SIUnitSymbolMicro m}}^{2}$ table compared to an SRAM implementation $235.2\text{\,}{\mathrm{\SIUnitSymbolMicro m}}^{2}$ (see \SIsection3 for details).

To evaluate the search energy improvement with an analog CAM, we simulated the circuit current from all the power supplies with an 86$\times$12 analog CAM array. For a practical evaluation of all digital applications, we custom designed a digital-to-analog (DAC) converter, which imposes additional overhead in both chip area and energy, but our analyses in \SInote3, \SIfigure17 and \SItable2 show this overhead is limited to approximately 10%. The cumulative consumed energy is calculated by integrating the voltage and current over the 16-cycle search with all MLs discharging in the search for the worst-case scenario. Estimating the full array power (including drivers and unoptimized peripherals such as the custom-designed digital-to-analog (DAC) converters), the average total energy per search is $\sim$ $0.52\text{\,}\mathrm{fJ}$ per analog cell, or $0.037\text{\,}\mathrm{fJ}$ for the equivalent number of TCAM bits implementing the same function (see \SInote3 for details). The energy per cell consumption is significantly smaller than an SRAM TCAM (0.165 fJ)[36], which utilizes numerous power saving techniques that provides a $>10\times$ reduction but are not implemented in our analog CAM yet, and a conventional memristor TCAM (0.17 fJ)[37].

In addition to serving as a higher data-density digital replacement, the proposed analog CAM offers novel applications when the range search capability is utilized. As an example, a decision tree with binary and non-binary classification features can be implemented in the analog CAM directly by mapping each root to leaf path to a row in the analog CAM (see \SIfigure18 and \SInote3 for mapping details). Logically, each root-to-leaf path traverses a series of nodes with Boolean ANDs between elements in a given input feature vector (\SIfigure18a). Since AND is commutative, we can reorder the nodes such that feature variables are processed in the same order for all paths[38]. Nodes for the same feature are combined into one node and “don’t care” nodes can be inserted for features absent from a specific path, such that each path is of equal length. This representation can then be directly mapped to the analog CAM array, with each root to leaf path a row. As the matching row can directly drive the readout of the classification result, tree traversal becomes a one-cycle operation (\SIfigure18b). This high throughput and low latency operation are highly advantageous and differentiated from current usage. While ensemble tree-based models are a popular state-of-the-art machine learning approach for classification and regression across diverse real-world applications, these models are difficult to optimize for fast runtime without accuracy loss in standard architectures[32] due to non-uniform memory access patterns, resulting in unpredictable traversal and classification times today. With our proposed analog CAM, it becomes feasible to process large tree-based models at high data rates, such as those required for streaming applications or autonomous vehicles.

0.5 Discussion

In summary, we have proposed an analog CAM cell circuit taking advantage of the analog memristor conductance tunability for the first time. A practical circuit implementation composed of six transistors and two memristors has been demonstrated in both experiment and simulation. The analog CAM increases memory density significantly, as one analog CAM cell can store multiple bits with only six transistors while an SRAM CAM cell stores 1 bit values with 10 transistors, or ternary values with 16 transistors in a TCAM cell. The analog capability opens up the possibility for directly processing analog signals acquired from sensors, and is particularly attractive for Internet of Things applications due to the potential low power and footprint. The output of the analog CAM after the sense amplifiers is digital, and thus can also remove the analog-digital conversion cost entirely. Finally, the functionality of our analog CAM with interval storage is intrinsically different from digital CAMs, which may enable new computing applications in decision tree models, associative computing and probabilistic processing where inexact compares and real-valued analog transition probabilities are common.

{methods}

0.6 Memristor integration

The memristors are monolithically integrated on CMOS fabricated in a commercial foundry in a $180\text{\,}\mathrm{nm}$ technology node. The integration starts with a removal of native oxide on the surface metal with reactive ion eaching (RIE) and a buffered oxide etch (BOE) dip. Chromium and platinum are then sputtered and patterned with E-beam lithography as the bottom electrode, followed by reactive sputtered $2\text{\,}\mathrm{nm}$ tantalum oxide as switching layer and sputtered tantalum metal as the top electrode. The device stack is finalized by sputtered platinum for passivation and improved electrical conduction.

0.7 Circuit simulation for analog CAM cell and arrays

The proposed 6T2M analog CAM cells designed in the Cadence Virtuoso Custom IC design environment (version ICADV12.1-64b.500.14), and the simulation result is analyzed and post-processed with HP-SPICE (version 4.11). The simulations utilize the TSMC $16\text{\,}\mathrm{nm}$ library and the designs follow the corresponding rules. The voltage parameters and timing diagram are shown in \SIfigure7. A custom python script generates the netlist for analog CAM arrays with different numbers of rows and columns and arbitrary configured memristor conductances and input voltages. In the netlist, the parasitic parameters are extracted from the taped out layout, including the wire resistance $1.91\text{\,}\mathrm{\SIUnitSymbolOhm}$, $2.27\text{\,}\mathrm{\SIUnitSymbolOhm}$, $0.85\text{\,}\mathrm{\SIUnitSymbolOhm}$ per block for ML, DL, SL, and capacitance $0.227\text{\,}\mathrm{fF}$, $0.324\text{\,}\mathrm{fF}$, $0.454\text{\,}\mathrm{fF}$ between different analog CAM cells. The voltage stimulus is always applied to the nodes that are the furthest from the ML sensing node, so that the impact of the wire resistance is the most significant, i.e. the worst case scenario.

0.8 Electrical characterization

The electrical characterization is conducted with a semiconductor parameter analyzer (Keysight B1500A) and Cascade probe station under room temperature. The conductance programming is performed with quasi-static direct-current (DC) sweeps, and where the current through the device is limited and controlled by the series connected transistor. After programming, the memristor conductance is readout by applying a small voltage across the memristor with the series-connected transistor fully turned on. The search operation is conducted by applying and sensing voltages from the corresponding node to/from a source measurement unit (SMU) on the B1500A. A custom python code with PyVISA library was used to control the equipment.

Data availability

The data supporting plots within this paper and other findings of this study are available with reasonable requests made to the corresponding author.