Low-power All-analog Circuit for Rectangular-type Analog Joint Source Channel Coding

TL;DR

This paper presents a low-power, all-analog circuit design for efficient Analog Joint Source Channel Coding (AJSCC) using Voltage Controlled Voltage Sources, suitable for wireless sensor networks with low power constraints.

Contribution

It introduces a novel all-analog rectangular-type AJSCC circuit realized with VCVS, verified through simulations and hardware implementations.

Findings

Feasible for low-power wireless sensor networks

Verified by Spice simulations and hardware tests

Achieves efficient signal compression with controlled distortion

Abstract

A low-complexity all-analog circuit is proposed to perform efficiently Analog Joint Source Channel Coding (AJSCC), which can compress two or more sensor signals into one with controlled distortion while also being robust against wireless channel impairments. The idea is to realize the rectangular-type AJSCC using Voltage Controlled Voltage Sources (VCVS). The proposal is verified by Spice simulations as well as breadboard and Printed Circuit Board (PCB) implementations. Results indicate that the design is feasible for low-complexity systems like persistent wireless sensor networks requiring low circuit power.

Full text

I Introduction

Analog Joint Source Channel Coding (AJSCC) [1] can compress two or more sensor signals into one with controlled distortion while also being robust against wireless channel impairments. AJSCC adopts Shannon mapping as its encoding method [2]. Such mapping, in which the design of rectangular (parallel) lines can be used for 2:1 compression (Fig. 1), was first introduced by Shannon in his seminal 1949 paper [3]. Later work has extended this mapping to a spiral type as well as to N:1 mapping [4]. AJSCC achieves optimal performance in rate-distortion ratio, whereas to achieve such optimality using separate source and channel coding, complex encoding/decoding and long block-length codes would be required, causing delays and energy inefficiencies. Shannon mapping has the two-fold property of (1) compressing the sources (by means of N:1 mapping) and (2) being robust to wireless channel distortions as the noise only introduces errors along the parallel lines (or the spiral curve). In contrast, linear mapping techniques such as Quadrature Amplitude Modulation (QAM) have errors spread on the entire constellation plane. Therefore, channel noise has less effect on the error performance for Shannon mapping as compared with linear modulation schemes. AJSCC requires simple compression and coding, and low-complexity decoding. In rectangular-type mapping, to compress the source signals (“sensing source point”), say Humidity and Temperature voltages ($V_{H}$, $V_{T}$), the point on the space-filling curve with minimum Euclidean distance from the source point is chosen (“AJSCC mapped point”), as illustrated in Fig. 1, via a simple projection on the curve. The transmitted signal is then the “accumulated length” of the lines from the origin to the mapped point, where the error introduced by the mapping is controlled by the spacing $\Delta_{H}$ between lines.

**Existing AJSCC Circuits: **Existing AJSCC solutions use all-digital hardware, and are power demanding and of high circuit complexity. For example, a Software-Defined Radio (SDR) system to realize AJSCC mapping has been reported in [5]. The mapping was also recently implemented in an optical digital communication system in [6]. Shannon-mapping encoding was adopted in [7] for a digital video transmission. No existing work has implemented AJSCC using an all-analog, low-complexity design, which is indeed needed for critical futuristic applications requiring low-power sensing such as persistent wireless sensor networks and Internet of Things (IoTs), where the sensing circuit is expected to occupy small space, consume very low power, and be inexpensive.

**Our Proposal: **We are proposing a novel all-analog circuit to realize AJSCC and to achieve the objective of very low circuit complexity and power consumption. The proposal is based on the observation that the voltage of each level can be generated by Voltage Controlled Voltage Sources (VCVS), which output a voltage that is proportional to the input voltage; also, these sources can be switched on or off based on the input signal. Our contributions can be summarized as follows:

• •

Proposing the first all-analog circuitry for AJSCC for low-complexity and low-power applications;

• •

Verifying the circuitry and assessing its performance via Spice simulations as well as by prototype development via breadboard and Printed Circuit Board (PCB) hardware implementations.

**Paper Outline: **In Sect. II, we present our all-analog circuit realization of AJSCC; then, in Sect. III, we provide the circuit performance results from both Spice simulations and implementations; finally, in Sect. IV, we draw the conclusions.

II All-analog Circuit Realization of AJSCC

Our proposed analog circuit is depicted in Fig. 2. The VCVS accepts voltage as input, and outputs a voltage that is a function of the input voltage. By observing the rectangular-mapping curve (see Fig. 1), there are two types of output increments. In the first (which we call Type 1), the output $V_{O}$ increases linearly with increasing $V_{T}$, i.e., $V_{O,Type1}\propto V_{T}$. This happens when we traverse the curve from left to right on odd-numbered lines to reach the mapped point. In the second (Type 2), the output decreases linearly with increasing $V_{T}$, i.e., $V_{O,Type2}=V_{R}-V_{O,Type1}$, which corresponds to traversing the curve from right to left on even-numbered lines to reach the mapped point. We realize these two types of outputs using two types of VCVS, where the overall mapping output is the voltage summation of the activated VCVS blocks, which represents the accumulated length of the curve from the origin to the mapped point. Note that $V_{H}$ controls which VCVS levels/lines are activated, while $V_{T}$ controls the VCVS output, as mentioned above. A stack of analog switches is used to implement the former and also to control the output of all levels. The number of switches is determined by the mapping resolution sought ($\Delta_{H}$).

The first and second levels of the circuit are shown in Fig. 2, where the output of each level is controlled by the corresponding analog switch. Each switch has three inputs: $V_{R}+\Delta_{H}$, $GND$, and the output of either a Type-1 or Type-2 VCVS. $V_{R}$ is a fixed voltage proportional to the x-axis range of the curve. Odd or even numbered switches are connected to Type-1 or Type-2 outputs, respectively. The number of activated switches is determined by considering both $V_{H}$ and the chosen resolution $\Delta_{H}$. This also determines the activation voltage of each switch.

The switching logic is explained as follows: each switch is activated only if $V_{H}$ is greater than a certain value based on the switch’s level in the stack. If not activated, the output of the switch is connected to $GND$; if activated, the output is equal to the VCVS output within a certain range ($\Delta_{H}$) of $V_{H}$ above the activation voltage. Once $V_{H}$ exceeds this range, the switch outputs its saturation voltage of $V_{R}+\Delta_{H}$. Finally, a voltage adder adds the outputs of all the (activated) switches and sends this analog signal to the FM analog circuit for Radio Frequency (RF) transmission. We refer the two levels, consisting of a Type-1 and Type-2 circuitry, as a stage. Figure 2 represents the first stage, which performs the mapping for the first two parallel lines (from the bottom).

In summary, if the mapped point lies on an odd-numbered line i.e., if $V_{H}$ is mapped to an odd-numbered level $n$, then the output of the voltage adder will be $V_{O}=(n-1)(V_{R}+\Delta_{H})+V_{T}$; conversely, for an even level, the output will be $V_{O}=(n-1)(V_{R}+\Delta_{H})+(V_{R}-V_{T})$. As an example, for the highlighted point in Fig. 1, the output of the adder will be $3(V_{R}+\Delta_{H})+(V_{R}-V_{T})$. A Sallen-Key structure or a simple voltage divider can be used for Type-1 VCVS along with a subtractor for Type-2 VCVS, comparators can be used to detect $V_{H}$ range, and a simple multiplexer for analog switching.

III Circuit Performance Evaluation

To verify our design and to assess the performance of our AJSCC mapping circuit, we have carried out thorough Spice simulations as well as performed prototype development via breadboard and PCB hardware implementations.

**Spice Simulations: **The AJSCC mapping circuit has been simulated in Spice. As mentioned in Sect. II, our circuit consists of multiple identical stages stacked one on top of the other (i.e., hardware is duplicated). Each such stage consists of two levels – Type-1 and Type-2 VCVS-based circuitry. We considered a temperature sensor ($AD22100$) and humidity sensor ($HIH4000$) having range, respectively, $1.375-3.625~{}\mathrm{V}$ for $0-100^{\circ}C$, and $0.8-3.8~{}\mathrm{V}$ for $0-100\%$. We first subtract the non-zero offset from $V_{T}$’s range as it adds to the total mapped length without carrying information. We have also removed the offset from $V_{H}$ as it simplifies the design; consequently, the offset-removed voltages, $V_{T0}$ and $V_{H0}$, range in $[0,2.25]$ and $[0,3.0]~{}\mathrm{V}$, respectively. Just for simulation and implementation purposes, we considered a $10\%$ resolution in humidity giving us $\Delta_{H}=0.3~{}\mathrm{V}$. Since it is a second stage, Type 1 is in linear region (and Type 2 is OFF) when $0.45~{}\mathrm{V}<V_{H0}\leq 0.75~{}\mathrm{V}$ and Type 2 is in linear region (and Type 1 is in saturation) when $0.75~{}\mathrm{V}<V_{H0}\leq 1.05~{}\mathrm{V}$. These voltages are also shown in Fig. 1 for ease of understanding.

Figure 3 shows the detailed schematic of the second stage of our circuit simulated in LTSpice, a Spice simulation tool. While we have prototyped the entire system (Fig. 4), we have chosen to simulate only the second stage as the $V_{H0}$ mapping range of both levels is more general compared to the first stage where the Type 1 has half of this value (i.e., [math] to $0.15~{}\mathrm{V}$). Offset removal is done using an OpAmp-based subtractor circuit. In fact, we have used well-known OpAmp-based subtractors and non-inverting adders for all subtractor and adder functionalities. Both $V_{T}$ and $V_{H}$ offset-removal blocks are indicated in the schematic. $V_{H0}$ range comparison is achieved using comparator ICs. Reference voltages ($0.45$, $0.75$, and $1.05~{}\mathrm{V}$) for comparison are generated using a simple voltage-divider circuit, as shown in the figure. In each level (Type 1 or Type 2), the outputs of the comparators act as select lines for the analog multiplexer (switches), which receives three inputs, i.e., saturation voltage $V_{R}$, Type-1 VCVS output ($type1\_out$) for level 1 or Type-2 VCVS output ($type2\_out$) for level 2, and ground signal ($g$). Saturation voltage, $V_{R}$, is the output of Type-1 VCVS when the sensor senses the maximum temperature, i.e., when $V_{T0}=2.25~{}\mathrm{V}$. $V_{R}$ and $g$ signals are passed to the output of a Type-1 multiplexer when $V_{H0}\leq 0.45~{}\mathrm{V}$ and $V_{H0}>0.75~{}\mathrm{V}$, respectively. Similar statements hold for a Type-2 multiplexer. We have mentioned above the condition for $V_{H0}$ when Type-1 (or Type-2) outputs are passed to the multiplexer. Type-1 VCVS is implemented as a simple voltage-divider circuit with 1:5 ratio, which means $V_{R}=0.45~{}\mathrm{V}$ as $V_{T0,max}=2.25~{}\mathrm{V}$. The output of Type 1 is subtracted from $V_{R}$ to get the Type-2 output.

Lastly, the outputs of both multiplexers are added to give the final output of this second stage. Similar outputs from the other stages are added to be given as input to the FM modulator. $V_{R}=V_{1}$ is determined by the maximum allowed voltage input to the FM modulator. We used manufacturer-provided Spice models to capture real performance; on the other hand, we were also limited by them as there are very few such models. Linear Technology’s $LT1006$ and $LT1018$, and Analog Devices’ $ADG408$ have been used, respectively, for OpAmp, comparator, and analog multiplexer functionalities.

Figure 5(a) shows the output of second stage over its entire mappable range of $V_{T}$ and $V_{H}$. It can be seen that the output is almost zero when $V_{H}$ is below $1.25~{}\mathrm{V}$ and that, when $1.25<V_{H}\leq 1.55$, Type 1 mainly drives the output (with zero contribution from Type 2); conversely, when $1.55<V_{H}\leq 1.85$, Type 2 mainly drives the output (with $V_{R}$ contribution from Type 1); finally, when $V_{H}>1.85$, the output is $2V_{R}$ (i.e., $V_{R}$ from each VCVS). Note that these are the actual sensor output voltages and not offset-removed values. By this manner, this circuit captures and maps the sensor outputs in the range $1.25\leq V_{H}<1.85$ and $1.375\leq V_{T}\leq 3.625$. We can observe some saturation behaviors (output not being exactly zero) when both levels are inactive and at the beginning of Type-1 and Type-2 active modes, which we attribute to the saturation of the OpAmps.

**Breadboard and PCB Hardware Implementations: **We have also implemented this single stage on a breadboard to verify the reproducibility of the simulation results using real hardware. We found that the results were vey similar to our simulation counterparts, as depicted in Fig. 5(a), with less saturation effects in fact. Breadboard results motivated us to go even a step further and implement the full circuit (all stages) along with the RF part (as a COTS component) i.e., a full-fledged sensor on a PCB entirely designed by us (Fig. 4). This sensor consists of three major blocks – AJSCC encoding, DC-to-sine wave conversion circuit, and a RFIC module. The AJSCC encoding block takes temperature and humidity voltages as input, and outputs the AJSCC-encoded voltage. It implements 11 VCVS levels in total, as per the setup described above ($\Delta_{H}=0.3~{}\mathrm{V}$). The DC-to-sine wave block converts the AJSCC-encoded DC voltage to a sine wave, which will then be FM modulated and RF transmitted by the RFIC module. We have also designed a receiver consisting of a RFIC module and a NI Digital Acquisition (DAQ) system, and used LabView to process the decoded $V_{T}$ and $V_{H}$ values.

Figure 5(b) shows the sensor’s AJSCC-mapped voltage for varying $V_{T}$ (with $V_{H}$ held constant at $1.83~{}\mathrm{V}$), while Fig. 5(c) shows it for varying $V_{H}$ (with $V_{T}$ held constant at $1.71~{}\mathrm{V}$). As expected, when $V_{H}$ is fixed, we observe a linear increase in the AJSCC output as $V_{T}$ is increased within its range. This is because of the linear VCVS functionality. However, a step output is expected when $V_{T}$ is fixed while $V_{H}$ is varied within its range. This is because all those $V_{H}$ values between two threshold-level voltages are mapped to the same voltage. It can also been seen in both cases that the decoded AJSCC voltage is very close to the transmitted AJSCC voltage, i.e., $\hat{V}_{T}$ closely follows $V_{T}$, while, as expected, a step is observed in $\hat{V}_{H}$.

We measured our prototype’s performance when three sensors (Tx) communicate simultaneously to a digital Cluster Head (Rx) using Frequency Division Multiple Access (FDMA). Figure 6 plots the SDR vs CSNR, where the former is the Signal-to-Distortion Ratio, i.e., the inverse in logarithmic scale of the Mean Square Error (MSE); and the latter is the Channel Signal-to-Noise Ratio, i.e., the SNR of the baseband signal at the output of the receiver RF module. SDR and CSNR are plotted by varying the Tx-Rx distance (with $V_{T}$ and $V_{H}$ fixed). As CSNR increases the SDR also increases, indicating the improved signal reconstruction performance.

**Power and Cost Considerations: **State-of-the-art sensor nodes consume $\approx 0.5~{}\mathrm{mA}$ in active mode and a few $\mathrm{\mu A}$ in sleep mode with supply voltages in the range $1.8-3.0~{}\mathrm{V}$, i.e., $0.9-1.5~{}\mathrm{mW}$ without taking into account the radio power: the active power consumption is mainly due to the microcontroller and Analog-to-Digital (A/D) conversions. In contrast, our all-analog sensor does not use power-hungry A/D’s or microcontrollers. The current drawn by the AJSCC baseband circuitry (using COTS OpAmps, Multiplexers, etc.), i.e., the entire board excluding the RFIC module, is $\approx 3~{}\mathrm{mA}$ with a supply voltage of $5~{}\mathrm{V}$ (equivalent to $\approx 15~{}\mathrm{mW}$); the cost of the AJSCC PCB is about \25$. These numbers, which are high because of (1) the use of COTS components and (2) duplication of hardware for each stage, can be reduced *drastically* if Integrated Circuit (IC) design is adopted. While our implementation serves as feasibility study, we believe the power consumption can be reduced to$\approx 150~{}\mathrm{\mu W}$ if our circuit is redesigned using the latest nm-technology components (for OpAmps, Comparators, and Multiplexers).

Let us provide a rough estimate: our circuit in total (5 and half stages/11 levels) consists of 16 OpAmps, 17 Comparators, and 11 Multiplexers, where OpAmps are clearly the major contributors to the overall power consumption. There are many low-power designs proposed for these components. For example, a low-power OpAmp [8] consuming about $8~{}\mathrm{\mu W}$, a comparator [9] consuming about $12.7~{}\mathrm{nW}$, and an analog multiplexer ($ADG704$) consuming about $10~{}\mathrm{nW}$ can be used for our circuit resulting in a power consumption of $\approx\mathrm{130\mu W}$. We are also optimistic that the sensor cost would reduce to less than \5$ leveraging economies of scale via mass production using the latest IC technology. Achieving both goals will enable critical futuristic applications such as persistent wireless sensing and IoT-based solutions.

IV Conclusion and Future Work

To achieve low-power, low-complexity compression of sensor signals into one with controlled distortion, while also being robust against wireless channel impairments, we proposed a novel all-analog circuit for rectangular-type Analog Joint Source Channel Coding (AJSCC) using Voltage Controlled Voltage Sources (VCVS). The proposal is evaluated by Spice simulations as well as breadboard and PCB implementations. We will address the hardware duplication issue as future work.

**Acknowledgments: **We thank Rutgers ECE graduate student Priyank Bharad for helping with the implementation.