# Influence of interface dipole layers on the performance of graphene   field effect transistors

**Authors:** Naoka Nagamura, Hirokazu Fukidome, Kosuke Nagashio, Koji Horiba,, Takayuki Ide, Kazutoshi Funakubo, Keiichiro Tashima, Akira Toriumi, Maki, Suemitsu, Karsten Horn, and Masaharu Oshima

arXiv: 1907.03310 · 2019-07-09

## TL;DR

This study investigates how interface dipole layers at the graphene-SiO2 interface influence the electronic properties and performance of graphene field-effect transistors, highlighting the role of surface chemistry and electrostatic effects.

## Contribution

It provides detailed band alignment analysis and links interface dipoles to GFET performance, offering insights for device optimization.

## Key findings

- Hydrophilic SiO2 surfaces modulate graphene's electronic properties.
- Interface dipoles are crucial in determining GFET performance.
- Hysteresis in resistance is caused by dipole layer reversal under gate voltage.

## Abstract

The linear band dispersion of graphene's bands near the Fermi level gives rise to its unique electronic properties, such as a giant carrier mobility, and this has triggered extensive research in applications, such as graphene field-effect transistors (GFETs). However, GFETs generally exhibit a device performance much inferior compared to the expected one. This has been attributed to a strong dependence of the electronic properties of graphene on the surrounding interfaces. Here we study the interface between a graphene channel and SiO$_{2}$, and by means of photoelectron spectromicroscopy achieve a detailed determination of the course of band alignment at the interface. Our results show that the electronic properties of graphene are modulated by a hydrophilic SiO$_{2}$ surface, but not by a hydrophobic one. By combining photoelectron spectromicroscopy with GFET transport property characterization, we demonstrate that the presence of electrical dipoles in the interface, which reflects the SiO$_{2}$ surface electrochemistry, determines the GFET device performance. A hysteresis in the resistance vs. gate voltage as a function of polarity is ascribed to a reversal of the dipole layer by the gate voltage. These data pave the way for GFET device optimization.

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Source: https://tomesphere.com/paper/1907.03310