Prototype of a transient waveform recording ASIC

TL;DR

This paper introduces a 0.18 μm CMOS ASIC prototype for transient waveform recording, featuring high sampling speed, wide bandwidth, and precise timing calibration, suitable for high-speed signal analysis.

Contribution

The paper presents a novel ASIC design with high-speed sampling, wide bandwidth, and improved timing resolution using calibration techniques.

Findings

Sampling speed adjustable from 0.076 to 3.2 Gsps

Input bandwidth approximately 450 MHz

Timing precision better than 15 ps RMS

Abstract

The paper presents the design and measurement results of a transient waveform recording ASIC based on the Switched Capacitor Array (SCA) architecture. This 0.18 {\mu}m CMOS prototype device contains two channels and each channel employs a SCA of 128 samples deep, a 12-bit Wilkinson ADC and a serial data readout. A series of tests have been conducted and the results indicate that: a full 1 V signal voltage range is available, the input analog bandwidth is approximately 450 MHz and the sampling speed is adjustable from 0.076 to 3.2 Gsps (Gigabit Samples Per Second). For precision waveform timing extraction, careful calibration of timing intervals between samples is conducted to improve the timing resolution of such chips, and the timing precision of this ASIC is proved to be better than 15 ps RMS.