Efficient Circuit Simulation in MapReduce

TL;DR

This paper establishes a theoretical connection between the computational power of MapReduce and Boolean circuit models, showing that many problems in NC can be efficiently solved in MapReduce with constant rounds.

Contribution

It develops a simulation technique that relates NC complexity classes to MapReduce, demonstrating that NC problems can be solved in a constant number of rounds within MapReduce.

Findings

NC problems can be simulated in MapReduce in O(T(n)/log n) rounds

NC^(i+1) is contained in DMRC^i for all i

Problems like integer multiplication and division are solvable in constant MapReduce rounds

Abstract

The MapReduce framework has firmly established itself as one of the most widely used parallel computing platforms for processing big data on tera- and peta-byte scale. Approaching it from a theoretical standpoint has proved to be notoriously difficult, however. In continuation of Goodrich et al.'s early efforts, explicitly espousing the goal of putting the MapReduce framework on footing equal to that of long-established models such as the PRAM, we investigate the obvious complexity question of how the computational power of MapReduce algorithms compares to that of combinational Boolean circuits commonly used for parallel computations. Relying on the standard MapReduce model introduced by Karloff et al. a decade ago, we develop an intricate simulation technique to show that any problem in NC (i.e., a problem solved by a logspace-uniform family of Boolean circuits of polynomial size and a depth polylogarithmic in the input size) can be solved by a MapReduce computation in O(T(n)/ log n) rounds, where n is the input size and T(n) is the depth of the witnessing circuit family. Thus, we are able to closely relate the standard, uniform NC hierarchy modeling parallel computations to the deterministic MapReduce hierarchy DMRC by proving that NC^(i+1) is contained in DMRC^i for all natural i, including 0. Besides the theoretical significance, this result that has important applied aspects as well. In particular, we show for all problems in NC^1---many practically relevant ones such as integer multiplication and division, the parity function, and recognizing balanced strings of parentheses being among these---how to solve them in a constant number of deterministic MapReduce rounds.

Equations

$${\mu }_1(⟨p;(x_{i_p},f_p,g_p)⟩)$$

$${\mu }_1(⟨q;(p_{q,j},x_{q,j},v_{q,j})⟩)$$

$$y(j)=$$

$$+s_{(\log q)-1}((j+1-2^{(\log q)-1})÷2^{(\log q)-1})\cdot a_{(\log q)-1}^j$$

$$+\dots$$

$$+s_1((j+1-2^1)÷2^1)\cdot a_1^j$$

$$+s_0((j+1-2^0)÷2^0)\cdot a_0^j;$$

$${\mu }_1(⟨j;(\text{level}(v),v)⟩)=\{⟨j÷\beta ;(j,\text{level}(v),v)⟩\}$$

$$\displaystyle\mu_{1}(\langle i;(\,(j,\textnormal{level}(v),v),(j^{\prime},\textnormal{level}(v^{\prime}),v^{\prime})\,)\rangle)=\{\$$

$$⟨j^{\prime }÷\beta ;((j,\text{level}(v),v),(j^{\prime },\text{level}(v^{\prime }),v^{\prime }))⟩\}$$

Full text

Efficient Simulation of Combinational Circuits in MapReduce

Fabian Frei

  

Koichi Wada

Efficient Implementation of Combinational Circuits in MapReduce

Fabian Frei

  

Koichi Wada

Efficient Circuit Simulation in MapReduce

Fabian Frei

  

Koichi Wada

1 Introduction

Despite the overwhelming success of the MapReduce framework in the big data industry and the great attention it has garnered ever since its inception over a decade ago, theoretical results about it have remained scarce in the literature. In particular, it is very natural to ask how powerful exactly MapReduce computations are in comparison to the traditional models of parallel computations based on circuits, a question that has practical implications as well. The answers have proved to be very elusive, however. In this paper, we show how MapReduce programs can efficiently simulate circuits used for parallel computations, thus tying these two worlds together more tightly.

In this section we first provide an introduction to the concept of MapReduce, then present the related work, and finally describe our contribution. In Section 2, we will formally define the traditional models of parallel computing and the MapReduce model. In Section 3, we then derive our main results. Section 4 concludes the paper with a short summary and a discussion of our findings, outlining opportunities for future research.

1.1 Background and Motivation

In recent years the amount of data available and demanding analysis has grown at an astonishing rate. The amount of memory in commercially available servers has also grown at a remarkable pace in the past decade; it is now exceeding tera- and even peta-bytes. Despite the considerable advances in the availability of computational power, traditional approaches remain insufficient to cope with such huge amounts of data. A new form of parallel computing has become necessary to deal with these enormous quantities of available data. The MapReduce framework has been attracting great interest due to its suitability for processing massive data-sets. This framework was originally developed by Google [5], but an open source implementation called Hadoop has recently been developed and is currently used by over a hundred companies, including Yahoo!, Facebook, Adobe, and IBM [19].

MapReduce differs substantially from previous models of parallel computation in that it combines aspects of both parallel and sequential computation. Informally, a MapReduce computation can be described as follows.

The input is a set of key-value pairs $\langle k;v\rangle{}$. In a first step, the map step, each of these key-value pairs is separately and independently transformed into an entire set of key-value pairs by a map function $\mu$. In the next step, the shuffle step, we collect all key-value pairs from the sets that have been produced in the previous step, group them by their keys, and merge each group $\{\langle k;v_{1}\rangle{},\langle k;v_{2}\rangle{},\ldots\}$ of pairs containing the same key into a single key-value pair $\langle k;\{v_{1},v_{2},\ldots\}\rangle{}$ consisting of said key and a list of the associated values. In a third step, the reduce step, a reduce function $\rho$ transforms the list of values in each key-value pair $\langle k;\{v_{1},v_{2},\ldots\}\rangle{}$ into a new list $\{v_{1}^{\prime},v_{2}^{\prime},\dots\}$. Again, this is done separately and independently for each pair. The final output consists of the pairs $\{\langle k;v_{1}^{\prime}\rangle{},\langle k;v_{2}^{\prime}\rangle{},\ldots\}$ for each key $k$. The different instances that implement the reduce function for the different groups of pairs are called reducers. Analogously, mappers are instances of the map function.

The three steps described above constitute one round of the MapReduce computation and transform the input set into a new set of key-value pairs. A complete MapReduce computation consists of any given number of rounds and acts just as the composition of the single rounds. The shuffle step works the same way every time; the map and reduce functions, however, may change from round to round. A MapReduce computation with $R$ rounds is therefore completely described by a list $\mu_{1},\rho_{1},\mu_{2},\rho_{2},\ldots,\mu_{R},\rho_{R}$ of map and reduce functions. In both the map step and the reduce step, the input pairs can be processed in parallel since the map and reduce functions act independently on the pairs and groups of pairs, respectively. These steps therefore capture the parallel aspect of a MapReduce computation, whereas the shuffle step enforces a partial sequentiality since the shuffled pairs can be output only once the previous map step is completed in its entirety.

The MapReduce paradigm has been introduced in [5] in the context of algorithm design and analysis. A treatment as a formal computational model, however, was missing in the beginning. Later on, a number of models have emerged to deal more rigorously with algorithmic issues [8, 10, 11, 14, 15]. In this paper, our interest lies in studying the MapReduce framework from a standpoint of parallel algorithmic power by comparing it to standard models of parallel computation such as Boolean circuits and parallel random access machines (PRAMs). A PRAM can be classified by how far simultaneous access by processors to its memory is restricted; it can be CRCW, EREW, CREW, or ERCW, where R, W, C, and E stand for Read, Write, Concurrent, and Exclusive, respectively [4]. If concurrent writing is allowed, we need to further specify how parallel writes by multiple processors to a single memory cell are handled. The most natural choice is arguably that every memory cell contains after each time step the total of all numbers assigned to it by different processors during that step. In fact, all constructions in this paper work with this treatment of simultaneous writes; we thus generally assume this model. If the context warrants it, we speak of a Sum-CRCW to make this assumption explicit.

1.2 Related Work

We briefly present and discuss the following known results on the comparative power of the MapReduce framework and PRAM models.

A $T$-time EREW-PRAM algorithm can be simulated by an $O(T)$-round MapReduce algorithm, where each reducer uses memory of constant size and an aggregate memory proportional to the amount of shared memory required by the PRAM algorithm [10, 11]. 2. 2.

A $P$-processor, $M$-memory, $T$-time EREW-PRAM algorithm can be simulated by an $O(T)$-round, $(P+M)$-key MUD algorithm with a communication complexity of $O(\log(P+M))$ bits per key, where a MUD (massive, unordered, distributed) algorithm is a data-streaming MapReduce algorithm in the following sense: The reducers do not receive the entire list of values associated with a given key at once, but rather as a stream to be processed in one pass, using only a small working memory determining the communication complexity [8]. 3. 3.

When using MapReduce computations to simulate a CRCW-PRAM instead, again with $P$ processors and $M$ memory, we incur an $O(\log_{m}(P+M))$ slowdown compared to the simulations above, where $m$ is an upper bound on each reducer’s input and output [10].

These results imply that any problem solved by a PRAM with a polynomial number of processors and in polylogarithmic time $T$ can be simulated by a MapReduce computation with an amount of memory equal to the number of PRAM processors, and in a number of rounds equal to the computation time of even the powerful CRCW-PRAM. Since the class of problems solved by CRCW-PRAMs in time $T\in O(\log^{i}n)$ is equal to the class of problems solved by families of polynomial-sized combinational circuits consisting of gates with unbounded fan-in and fan-out and time $T\in O(\log^{i}n)$ (often denoted $\mathcal{A}\hskip 1.00006pt\mathcal{C}^{i}$) [1], these circuits can be simulated in a MapReduce computation with a number of rounds equal to the time required by these circuits.

Since the publication of the seminal paper by Karloff et al. [11], extensive effort has been spent on developing efficient algorithms in MapReduce-like frameworks [3, 6, 13, 12, 17]. Only few relationships between the theoretical MapReduce model [11] and classical complexity classes have been established, however; for example, any problem in $\mathcal{SP}\mathcal{A}\hskip 0.80002pt\mathcal{C}\mathcal{E}(o(\log n))$ can be solved by a MapReduce computation with a constant number of rounds [7].

Recently, Roughgarden et al. [16, Theorem 6.1] described a short and simple way of simulating $\mathcal{N}\mathcal{C}^{1}$ circuits with a certain class of models of parallel computation. The constraints of these models, namely the number of machines and the memory restrictions, are exactly tailored to allow for this general simulation method, however. In particular, it crucially relies on the fact that all models of this class are more powerful than the MapReduce model in that they all grant us a number of machines that is polynomial in the input size; this makes it possible to just dedicate one machine to each of the circuit gates. Such a simple simulation is impossible with MapReduce computations since the standard model due to Karloff only allows for a sublinear number of machines with sublinear memory.

1.3 Contribution

We prove that $\mathcal{N}\mathcal{C}^{i+1}\subseteq\mathcal{D}\mathcal{M}\mathcal{R}\hskip 1.00006pt\mathcal{C}^{i}$ for all $i\in\{0,1,2,\dots\}$, where $\mathcal{D}\mathcal{M}\mathcal{R}\hskip 1.00006pt\mathcal{C}^{i}$ is the set of problems solvable by a deterministic MapReduce computation in $O(\log^{i}n)$ rounds. In the case of $\mathcal{N}\mathcal{C}^{1}\subseteq\mathcal{D}\mathcal{M}\mathcal{R}\hskip 1.00006pt\mathcal{C}^{0}$, which already opens up a plethora of applications on its own, the result holds for every possible choice of $\varepsilon$, that is, for $0<\varepsilon\leq 1/2$. The higher levels of the hierarchy require an entirely different proof method, which yields the result for $0<\varepsilon<1/2$.

This is a substantial improvement over the previous results that only imply, as outlined above, the far weaker claim $\mathcal{A}\hskip 1.00006pt\mathcal{C}^{i}\subseteq\mathcal{M}\mathcal{R}\hskip 1.19995pt\mathcal{C}^{i}$. The case $i=1$ is of particular practical interest since $\mathcal{N}\mathcal{C}^{1}\setminus\mathcal{A}\hskip 1.00006pt\mathcal{C}^{0}$ contains plenty of relevant problems such as integer multiplication and division, the parity function, and the recognition of the Dyck languages $D_{n}$, which contain all balanced strings of $n$ different types of parentheses; see [1]. Our results show how to solve all of these problems with a deterministic MapReduce program in a constant number of rounds.

2 Preliminaries

We denote by $\mathbb{N}=\{0,1,2,\ldots\}$ the natural numbers including zero and let $\mathbb{N}_{+}=\mathbb{N}\setminus\{0\}$. Moreover, we let $[i]=\{0,1,\ldots,i-1\}$ denote the $i$ first natural numbers for any $i\in\mathbb{N}_{+}$.

2.1 Models of Parallel Computation

In this section, we define the common complexity classes capturing the power of parallel computation; most prominently the $\mathcal{N}\mathcal{C}$ hierarchy.

A finite set $\mathcal{B}=\{f_{0},\ldots,f_{|\mathcal{B}|-1}\}$ of Boolean functions $f_{i}:\{0,1\}^{n_{i}}\rightarrow\{0,1\}$ with $n_{i}\in\mathbb{N}$ for every $i\in[|\mathcal{B}|]$ is called a basis. For every $n,m\in\mathbb{N}_{+}$, a (Boolean) circuit $C$ over the basis $\mathcal{B}$ with $n$ inputs and $m$ outputs is a directed acyclic graph that contains $n$ sources (nodes with no incoming edges), called the input nodes, and $m$ sinks (nodes with no outgoing edges). The fan-in of a node is the number of incoming edges, the fan-out is the number of outgoing edges. Nodes that are neither sources nor sinks are called gates. Each gate is labeled with a function $f_{i}\in\mathcal{B}$ and has fan-in $n_{i}$. It computes $f_{i}$ on the input given by the incoming edges and outputs the result (either 0 or 1) to the outgoing edges. A basis $\mathcal{B}$ is said to be complete if for every Boolean function $f$, we can construct a circuit of the described form that computes $f$ over the basis $\mathcal{B}$. In the following, we use the complete basis $\mathcal{B}=\{\vee,\wedge,\neg\}$.

The size of a circuit $C$, denoted by $\textnormal{size}(C)$, is the total number of edges it contains. The level of a node $v$ in a circuit $C$, denoted $\textnormal{level}(v)$, is defined recursively: The level of a sink is [math], and the level of a node $v$ with nonzero fan-out is one greater than the maximum of the levels of the outgoing neighbors of $v$. The depth of $C$, denoted $0pt(C)$, is the maximum level across all nodes in $C$.

A function $f:\{0,1\}^{*}\rightarrow\{0,1\}^{*}$ is implicitly logspace computable if the two mappings $(x,i)\mapsto\chi_{i\leq|f(x)|}$, where $\chi$ denotes the characteristic function, and $(x,i)\mapsto(f(x))_{i}$ are computable using logarithmic space. A circuit family $\{C_{n}\}_{n=0}^{\infty}$ is logspace-uniform if there is an implicitly logspace computable function mapping $1^{n}$ to the description of the circuit $C_{n}$. It is known that the class of languages that have logspace-uniform circuits of polynomial size equals $\mathcal{P}$ [1, Thm. 6.15].

For any $i\in\mathbb{N}$, the complexity class $\mathcal{N}\mathcal{C}^{i}$ contains a language $L$ exactly if there is a constant $c$ and a logspace-uniform family of circuits $\{C_{n}\}_{n=0}^{\infty}$ recognizing $L$ such that $C_{n}$ has size $O(n^{c})$, depth $O(\log^{i}n)$, and all nodes have fan-in at most 2. The union is Nick’s class $\mathcal{N}\mathcal{C}=\bigcup_{i=0}^{\infty}\mathcal{N}\mathcal{C}^{i}$. We mention that there is an analogous definition of classes $\text{Nonuniform-}\mathcal{N}\mathcal{C}^{i}$ that do not require logspace uniformity from the circuits; they constitute a different hierarchy.

The complexity classes $\mathcal{A}\hskip 1.00006pt\mathcal{C}^{i}$ and $\mathcal{A}\hskip 1.00006pt\mathcal{C}=\bigcup_{i=0}^{\infty}\mathcal{A}\hskip 1.00006pt\mathcal{C}^{i}$ are defined exactly as $\mathcal{N}\mathcal{C}^{i}$ and $\mathcal{N}\mathcal{C}$, except that the restriction of the maximal fan-in to at most 2 is omitted. Nevertheless, the restriction on the circuit size imply that the fan-in of a node is bounded by a polynomial in $n$. The OR gates and AND gates in such a circuit can therefore be replaced by trees of gates of fan-in at most 2 with a depth in $O(\log n)$. It follows that $\mathcal{A}\hskip 1.00006pt\mathcal{C}^{i}\subseteq\mathcal{N}\mathcal{C}^{i+1}$ for all $i\in\mathbb{N}$ and thus $\mathcal{N}\mathcal{C}=\mathcal{A}\hskip 1.00006pt\mathcal{C}$. (Analogously, we see why Nick’s class can also be defined, as it often is, by upper-bounding the fan-in by an arbitrary constant greater than 2.) The inclusion $\mathcal{N}\mathcal{C}^{i}\subseteq\mathcal{A}\hskip 1.00006pt\mathcal{C}^{i}$ for every $i\in\mathbb{N}$ is immediate from the definition. The first two inclusions of the resulting chain are known to be strict—namely, we have $\mathcal{N}\mathcal{C}^{0}\subsetneq\mathcal{A}\hskip 1.00006pt\mathcal{C}^{0}\subsetneq\mathcal{N}\mathcal{C}^{1}$; see [1].

Finally, we summarize the known results on how the classes of languages recognized by different PRAMs fit into the two hierarchies of $\mathcal{N}\mathcal{C}$ and $\mathcal{A}\hskip 1.00006pt\mathcal{C}$. Let $\mathcal{E}\mathcal{R}\hskip 0.70007pt\mathcal{E}\mathcal{W}^{i}$, $\mathcal{C}\mathcal{R}\hskip 0.70007pt\mathcal{E}\mathcal{W}^{i}$ and $\mathcal{C}\mathcal{R}\hskip 0.70007pt\mathcal{C}\mathcal{W}^{i}$ denote the sets of problems of size $n$ computed by EREW-PRAMs, CREW-PRAM, and CRCW-PRAMs, respectively, with a polynomial number of processors in $O(\log^{i}n)$ time. For every $i\in\mathbb{N}$, we have $\mathcal{N}\mathcal{C}^{i}\subseteq\mathcal{E}\mathcal{R}\hskip 0.70007pt\mathcal{E}\mathcal{W}^{i}\subseteq\mathcal{C}\mathcal{R}\hskip 0.70007pt\mathcal{E}\mathcal{W}^{i}\subseteq\mathcal{C}\mathcal{R}\hskip 0.70007pt\mathcal{C}\mathcal{W}^{i}=\mathcal{A}\hskip 1.00006pt\mathcal{C}^{i}\subseteq\mathcal{N}\mathcal{C}^{i+1}$; see [1].

2.2 The MapReduce Model

In this section we describe the standard MapReduce model as proposed Karloff et al. [11]. It defines the notions of map functions and reduce functions, which are summarized under the term primitives. Roughly speaking, a MapReduce computing system executes primitives, interleaved with so-called shuffle operations. The basic data unit in these computations is an ordered pair $\langle key;value\rangle$, called key-value pair. In general, keys and values are just binary strings, allowing us to encode all the usual entities.

A map function is a (possibly randomized) function that takes as input a single key-value pair and outputs a finite multiset of new key-value pairs. A reduce function (again, possibly randomized) takes instead an entire set of key-value pairs $\{\langle k;v_{k,1}\rangle,\langle k;v_{k,2}\rangle,\ldots\}$, where all the keys are identical, and outputs a single key-value pair $\langle k;v^{\prime}\rangle$ with that same key.

A MapReduce program is nothing else than a sequence $\mu_{1},\rho_{1},\mu_{2},\rho_{2},\ldots,\mu_{R},\rho_{R}$ of map functions $\mu_{r}$ and reduce functions $\rho_{r}$. The input of this program is a multiset $U_{0}$ of key-value pairs. For each $r\in\{1,\ldots,R\}$, a map step, a shuffle step and a reduce step are successively executed as follows:

Map step: Each pair $\langle k;v\rangle$ in $U_{r-1}$ is given as input to an arbitrary instance of the map function $\mu_{r}$, which then produces a finite sequence of pairs. The multiset of all produced pairs is denoted by $U^{\prime}_{r}$. 2. 2.

Shuffle step: For each key $k$, let $V_{k,r}$ be the multiset of all values $v_{i}$ such that $\langle k,v_{i}\rangle{}$. The MapReduce system automatically constructs the multiset $V_{k,r}$ from $U^{\prime}_{r}$ in the background. 3. 3.

Reduce step: For each key $k$, a reducer (i.e., an instance calculating the reduce function $\rho_{r}$) receives $k$ and the elements of $V_{k,r}$ in arbitrary order. We usually write such an input as a set of key-value pairs that all have key $k$. The reducer calculates from $V_{k,r}$ another multiset $V_{k,r}^{\prime}$, which is output in the form of one key-value pair $\langle k,v^{\prime}\rangle$ for each $v^{\prime}$ in $V_{k,r}^{\prime}$.

Fix any $\varepsilon$ with $0<\varepsilon\leq 1/2$ and denote the size of the MapReduce program’s input by $N$. For every $i\in\mathbb{N}$, a problem is in $\mathcal{M}\mathcal{R}\hskip 1.19995pt\mathcal{C}^{i}$ if and only if if there is a MapReduce program $\mu_{1},\rho_{1},\mu_{2},\rho_{2},\ldots,\mu_{R},\rho_{R}$ satisfying the following properties:

It outputs a correct answer to the problem with probability at least $3/4$. 2. 2.

The number of rounds of the MapReduce program, $R$, is in $O(\log^{i}N)$. 3. 3.

The potentially randomized primitives (i.e., all map and reduce functions) are computable by a RAM with $O(\log N)$-bit words using $O(N^{1-\varepsilon})$ space and time polynomial in $N$. 4. 4.

The pairs produced by the map functions can be stored in $O(N^{2(1-\varepsilon)})$ space.

A MapReduce program satisfying these conditions is called an $\mathcal{M}\mathcal{R}\hskip 1.19995pt\mathcal{C}^{i}$-algorithm. Note that due to the last condition it is impossible to even store the input unless $2(1-\varepsilon)\geq 1$, which explains the restriction to $0<\varepsilon\leq 1/2$. As with $\mathcal{N}\mathcal{C}$, we define the union class $\mathcal{M}\mathcal{R}\hskip 1.19995pt\mathcal{C}=\bigcup_{i=0}^{\infty}\mathcal{M}\mathcal{R}\hskip 1.19995pt\mathcal{C}^{i}$. Requiring all primitives to be deterministic yields the analogous hierarchy of $\mathcal{D}\mathcal{M}\mathcal{R}\hskip 1.00006pt\mathcal{C}=\bigcup_{i=0}^{\infty}\mathcal{D}\mathcal{M}\mathcal{R}\hskip 1.00006pt\mathcal{C}^{i}$. Note that we obviously have $\mathcal{D}\mathcal{M}\mathcal{R}\hskip 1.00006pt\mathcal{C}^{i}\subseteq\mathcal{M}\mathcal{R}\hskip 1.19995pt\mathcal{C}^{i}$ for all $i\in\mathbb{N}$. We will often refer to the single rounds of such MapReduce algorithms as $\mathcal{M}\mathcal{R}\hskip 1.19995pt\mathcal{C}$-rounds and $\mathcal{D}\mathcal{M}\mathcal{R}\hskip 1.00006pt\mathcal{C}$-rounds, respectively.

3 Simulating Parallel Computations by MapReduce

We are now going to prove our two main results $\mathcal{N}\mathcal{C}^{1}\subseteq\mathcal{D}\mathcal{M}\mathcal{R}\hskip 1.00006pt\mathcal{C}^{0}$ for $0<\varepsilon\leq 1/2$ and $\mathcal{N}\mathcal{C}^{i+1}\subseteq\mathcal{D}\mathcal{M}\mathcal{R}\hskip 1.00006pt\mathcal{C}^{i}$ for all $i\in\mathbb{N}_{+}$ and $0<\varepsilon<1/2$ in Sections 3.2 and 3.3, respectively. In both cases, we will be making use of the technical tool derived in Section 3.1 and obtain the results by showing how to use MapReduce computations for two different, delicate simulations. For the inclusion $\mathcal{N}\mathcal{C}^{1}\subseteq\mathcal{D}\mathcal{M}\mathcal{R}\hskip 1.00006pt\mathcal{C}^{0}$, we simulate width-bounded branching programs that are equivalent to the respective circuits by Barrington’s classical theorem [2], whereas for the higher levels of the hierarchy, we directly simulate the combinational circuits themselves.

3.1 A Technical Tool

Goodrich et al. [10] parametrize MapReduce algorithms, on the one hand, by the memory limit $m$ for the input/output buffer of the reducers and, on the other hand, by the communication complexity $K_{r}$ of round $r$, that is, the total size of inputs and outputs for all mappers and reducers in round $r$. We state a useful result from [10].

Theorem 3.1**.**

Any CRCW-PRAM algorithm using $M$ total memory, $P$ processors and $T$ time can be simulated in $O(T\log_{m}P)$ deterministic MapReduce-rounds with communication complexity $K_{r}\in O((M+P)\log_{m}(M+P))$.

We denote by $N$ the size of the smallest circuit representation of the CRCW-PRAM algorithm (i.e., its number of edges) plus the size of its input. Taking into account our requirements $m\in O(N^{1-\varepsilon})$ and $K_{r}\in O(N^{2(1-\varepsilon)})$, we obtain the following a technical tool, which will prove to be useful in our endeavor.

Corollary 3.2**.**

Any CRCW-PRAM algorithm using $M$ total memory, $P$ processors and $T$ time can be simulated in $O(T\log_{N^{1-\varepsilon}}P)$ $\mathcal{D}\mathcal{M}\mathcal{R}\hskip 1.00006pt\mathcal{C}$-rounds if $(M+P)\log_{N^{1-\varepsilon}}(M+P)\in O(N^{2(1-\varepsilon)})$.

3.2 Simulating $\mathcal{N}\mathcal{C}^{1}$

It is known that $\text{Nonuniform-}\mathcal{N}\mathcal{C}^{1}$ is equal to the class of languages recognized by nonuniform width-bounded branching programs. A careful inspection of the proof due to Barrington [2]—crucially relying on the non-solvability of the permutation group on 5 elements—reveals that it naturally translates to the uniform analogue: Our uniform class $\mathcal{N}\mathcal{C}^{1}$ is identical with the class of languages recognized by uniform width-bounded branching programs. In order to prove $\mathcal{N}\mathcal{C}^{1}\subseteq\mathcal{D}\mathcal{M}\mathcal{R}\hskip 1.00006pt\mathcal{C}^{0}$, it therefore suffices to show how to simulate such branching programs by appropriate MapReduce computations with a constant number of rounds.

We first define width-bounded branching programs. Let $n,w\in\mathbb{N}_{+}$. The input to the program is an assignment $\alpha$ to $n$ Boolean variables $\mathcal{X}=\{x_{0},\ldots,x_{n-1}\}$. An instruction or line of the program is a triple $(x_{i},f,g)$, where $i$ is the index of an input variable $x_{i}\in\mathcal{X}$ and $f$ and $g$ are endomorphisms of $[w]$. An instruction $(x_{i},f,g)$ evaluates to $f$ if $\alpha(x_{i})=1$ and to $g$ if $\alpha(x_{i})=0$. A width-$w$ branching program of length $t$ is a sequence of instructions $(x_{i_{j}},f_{j},g_{j})$ for $j\in[t]$. We also refer to the $t$ instructions as the lines of the program. Given an assignment $\alpha$ to $\mathcal{X}$, a branching program $B$ yields a function $B(\alpha)$ that is the composition of the functions to which the instructions evaluate.

To recognize a language $L\subseteq\{0,1\}^{*}$, we need a family $(B_{n})_{n=0}^{\infty}$ of width-$w$ branching programs with $B_{n}$ taking $n$ Boolean inputs. We say that $L$ is recognized by $B_{n}$ if there is, for each $n\in\mathbb{N}$, a set $F_{n}$ of endomorphisms of $[w]$ such that for all $\alpha\in\{0,1\}^{n}$, $\alpha\in L$ if and only if $B_{n}(\alpha)\in F_{n}$. If $f_{i}$ and $g_{i}$ are automorphisms, that is, permutations of $[w]$ for all $i\in[t]$, then $B_{n}$ is called a width-$w$ permutation branching program, or $w$-PBP for short.

Theorem 3.3**.**

[2]** If $L\in\mathcal{N}\mathcal{C}^{1}$, then $L$ is recognized by a logspace-uniform $5$-PBP family.

Due to Theorem 3.3 it is sufficient for our purposes to simulate the $w$-PBPs with constant $w$ instead of the circuit families provided by the definition of $\mathcal{N}\mathcal{C}^{1}$. In order to do this, we need to encode the given $w$-PBP and the possible assignments in the right form, namely we express them as sets of key-value pairs. A $w$-PBP of length $t$ can be described as the set $\{\langle\,p;\,(x_{i_{p}},f_{p},g_{p})\,\rangle\mid p\in[t]\}$, where we call $p$ the line number of line $(x_{i_{p}},f_{p},g_{p})$. Similarly, an assignment $\alpha\colon\mathcal{X}\to\{0,1\},x_{i}\mapsto v_{i}$ to the input variables $\mathcal{X}=\{x_{0},x_{1},\ldots,x_{n-1}\}$ is described by the set of key-value pairs $\{\langle i;(x_{i},v_{i})\rangle\mid i\in[n]\}$, letting the mappers divide the information by the indices of the input variables. Let $N_{\textnormal{O}}$ and $N_{\textnormal{I}}$ be the total size of the encodings of the $w$-PBP and the input assignment $\alpha$, respectively. Let $N=N_{\textnormal{O}}+N_{\textnormal{I}}$ and let $d=\lceil N_{\textnormal{O}}^{1-\varepsilon}\rceil$ and $\ell=\lceil N_{\textnormal{O}}^{\varepsilon}\rceil$. We denote by $\div$ the integer division. For every $q\in[t\div{}d]$, let $w$-PBP​q be the $q$th of the subprogram blocks of $w$-PBP of length $d$, that is $\{\langle p;(x_{i_{p}},f_{p},g_{p})\rangle\mid qd\leq p\leq(q+1)d-1\}$. For ease of readability, we assume from now on without loss of generality that $d\ell=t$, so that $w$-PBP can be partitioned into exactly $\ell$ such subprograms.

For every $q\in[\ell]$, we denote by $\mathcal{X}_{q}$ the subset of variables from $\mathcal{X}$ appearing in the instructions of subprogram $w$-PBP​q. An assignment $\alpha_{q}\colon\mathcal{X}_{q}\to\{0,1\}$ to these variables is represented as a set of key-value pairs in the following way. Recall that the subprogram $w$-PBP​q is a list of lines, each of which requires the assignment of a value, either 0 or 1, for exactly one variable. Let $x_{q,j}$ be the $j$th variable to which a value is assigned in $w$-PBP​q, let $p_{q,j}$ denote the number of the line in which this assignment occurs for the first time in $w$-PBP​q, and let $v_{q,j}$ denote the value that is assigned to $x_{q,j}$ in this line. Now, we represent $\alpha_{q}$ by $\{\langle q;(p_{q,j},x_{q,j},v_{q,j})\rangle\mid j\in[|\mathcal{X}_{q}|]\}$. Note that despite the dependence of $\mathcal{X}_{q}$ on $q$, we always have $|\mathcal{X}_{q}|\leq d$. Having seen how to express $w$-PBP, $\alpha$, and both $w$-PBP​q and $\alpha_{q}$ for all $q\in[\ell]$ as a set of key-value pairs, we are ready to state and prove the following lemma.

Lemma 3.4**.**

Let $L$ be a $w$-PBP-recognized language. If, for every $q\in[\ell]$, the representations of $w$-PBP and $\alpha_{q}$ are given, then we can decide in a $2$-round $\mathcal{D}\mathcal{M}\mathcal{R}\hskip 1.00006pt\mathcal{C}$-computation whether $\alpha\in L$ or not.

Proof 3.5**.**

As already described above, let $w$-PBP be represented by the set $\{\langle p;(x_{i_{p}},f_{p},g_{p})\rangle\mid p\in[t]\}$ and, for every $q\in[\ell]$, the assignment $\alpha_{q}$ by $\{\langle q,(p_{q,j},x_{q,j},v_{q,j})\rangle\mid j\in[|\mathcal{X}_{q}|]\}$. Note that there are $\ell$ subprograms of length at most $d$ and $\ell$ partial assignments that each assign values to at most one variable per line of the corresponding partial program, thus the total size of the input is in $O(d\ell)\subseteq O(N_{\textrm{O}})\subseteq O(N)$.

We define the first map function $\mu_{1}$ by

[TABLE]

For any $q\in[\ell]$, there is one subprogram $w$-PBP​q and an associated assignment set $\alpha_{q}$. We use the map function $\mu_{1}$ to find the value assignment for each variable appearing in $w$-PBP​q and store it in a key-value pair. This pair has the key $q$ and is thereby designated to be processed by reducerq, which can calculate $\rho_{1}$, having all pairs with key $q$ available. This function simulates, for each permutation $\pi$ of $[w]$, the subprogram $w$-PBP​q on this permutation with the received assignment and stores the resulting permutation $\pi^{\prime}$. This yields a table $T_{q}$ of size $w!\in O(1)$, describing the action of $w$-PBP​q for the given assignment on all $w!$ permutations. (We mention in passing that for the first reducer0 it would be sufficient to compute and store only the permutation that results from applying $w$-PBP0 on the given assignment to the identity as the initial permutation, thus saving the time and memory necessary for the rest of the first table.) The output of $\rho_{1}$ on the $q$th reducer is $\langle q;T_{q}\rangle$.

The map function $\mu_{2}$ of the second round is simple, it maps $\langle q;T_{q}\rangle$ to $\langle 0;(q,T_{q})\rangle$, thus delivering all pairs $(i,T_{i})$ to a single instance of the reduce function $\rho_{2}$. This first reducer has therefore all tables $T_{0},\ldots,T_{\ell-1}$ at its disposal and knows which one is which. Using $T_{q}$ as a look-up table for the permutation performed by $w$-PBP​q, reducer0 can now compute, starting from the identity permutation id, the permutation $\pi=T_{\ell-1}\circ\dots\circ T_{2}\circ T_{1}\circ T_{0}(\textnormal{id})$, and the input is accepted if and only if $\pi\in F_{n}$, where $F_{n}$ is the set of accepted permutations that is given to us alongside the program $w$-PBP.

In the following four lemmas, we show that $\alpha_{q}$ can be computed in a constant number of rounds from $w$-PBP and $\alpha$ for every $q\in[\ell]$. The challenge lies in designing an interface between the different reducers to bridge the gap between the $\ell$ program blocks $w$-PBPq and the given assignments, initially cut into $\ell$ block based solely on the indices of the input variables, without exceeding the memory limits. We begin with a brief overview of the four steps.

For each $x_{i}$, where $i\in[n]$, we compute the number of subprograms in which $x_{i}$ appears, and denote this number by $\#S(x_{i})$. Note that $\#S(x_{i})\leq\ell$ and that $\#S(x_{i})$ is the number of all those reducers for which the value assignment of $x_{i}$ is generally required to compute the resulting permutations in the corresponding subprograms. 2. 2.

We compute the prefix sums of $\#S(x_{i})$. For $i\in[n]$, let $y_{i}=\sum_{j=0}^{i}\#S(x_{j})$. Note that $y_{i}$ is the number of assignment triples $(p_{q,j},x_{q,j},v_{q,j})$ with $0<j\leq i$ needed to compute the action of the first $i$ subprograms and that $y_{n-1}=\sum^{\ell-1}_{q=0}|\alpha_{q}|$. 3. 3.

Based on the prefix sums, we will compute a separation of the input variables into $\ell$ contiguous blocks such that, for each $q\in[\ell]$, it is feasible for reducerq to produce from the $q$th block the input value assignments that it needs to contribute for the next step. This is nontrivial since the number of input assignments must not exceed $O(d)$ due to the memory limitation of reducerq. A separation of the input variables $\{x_{0},\ldots,x_{n-1}\}$ is a list of $\ell-1$ split values $\sigma_{1},\ldots,\sigma_{\ell-1}$ such that we have $\ell$ ordered, contiguous blocks $\{x_{0},\ldots,x_{\sigma_{1}}\},\{x_{\sigma_{1}+1},\ldots,x_{\sigma_{2}}\},\ldots,\{x_{\sigma_{\ell-1}+1},\ldots,x_{n-1}\}$. For notational convenience, we let $\sigma_{0}=-1$ and $\sigma_{\ell}=n-1$. Let $\sigma_{q}=\max\{j\in[n]\mid y_{j}\leq qd\}$ for $q\in\{1,\ldots,\ell-1\}$. Using these split values, each reducerq can provide all value assignments needed for the computation of all subprograms in the next step without violating the memory limitations. 4. 4.

We compute $\alpha_{q}$ for $q\in[\ell]$ by using $w$-PBP, the input assignment $\alpha$, and the split values.

Lemma 3.6**.**

Calculating $\#S(x_{i})$ is in $\mathcal{D}\mathcal{M}\mathcal{R}\hskip 1.00006pt\mathcal{C}^{0}$. That is, for each $i\in[n]$, $\#S(x_{i})$ is computable from $w$-PBP in a constant number of $\mathcal{D}\mathcal{M}\mathcal{R}\hskip 1.00006pt\mathcal{C}$-rounds.

Proof 3.7**.**

For each $q\in[\ell]$, the subprogram $w$-PBP​q is stored in reducerq. The output of reducerq—which will be the input to compute $\#S(x_{i})$—is $\langle q;(q,1)\rangle,\ldots,\langle q;(q,k_{q})\rangle$, with the variables $x_{q,1},\ldots,x_{q,k_{q}}$ appearing in the subprogram $w$-PBP​q and $k_{q}\in O(d)$. The total number of inputs used to compute $\#S(x_{i})$ is therefore at most $d\ell\in O(N)$. We use a Sum-CRCW-PRAM, whose concurrent writes to a single memory register are resolved by summing up all values being written to the same register simultaneously, see [10]. We use at most $d\ell$ processors, $\textrm{P}\!_{q,1},\ldots,\textrm{P}\!_{q,k_{q}}$ for each $q\in[\ell]$, and registers $\textrm{R}_{0},\ldots,\textrm{R}_{n-1}$ and let all processors $\textrm{P}\!_{q,j}$ add $1$ to $\textrm{R}_{j}$ concurrently. Thus we see that the computing $\#S(x_{i})$ is possible in constant time on a Sum-CRCW-PRAM and therefore, by Corollary 3.2, in $\mathcal{D}\mathcal{M}\mathcal{R}\hskip 1.00006pt\mathcal{C}^{0}$.

Lemma 3.8**.**

Computing the prefix-sums of $\#S(x_{i})$ is in $\mathcal{D}\mathcal{M}\mathcal{R}\hskip 1.00006pt\mathcal{C}^{0}$.

Proof 3.9**.**

The input is given as $\langle i;(\#S(x_{i}),i)\rangle$ for $i\in[n]$. We compute the prefix-sums $y_{i}$ of $\#S(x_{i})$ for all $i\in[n]$ in three rounds that can be summarized as follows:

Each reducerq, for $q\in[\ell]$, determines its local prefix-sums; that is, it computes the $d$ prefix-sums $y^{\textnormal{local}}_{dq},\ldots,y^{\textnormal{local}}_{d(q+1)-1}$ of the $d$ numbers $\#S(x_{dq}),\ldots,\#S(x_{d(q+1)-1})$. 2. 2.

A single reducer computes the prefix-sums $z_{0},z_{1},\ldots z_{\ell-1}$ of $y^{\textnormal{local}}_{d-1},y^{\textnormal{local}}_{2d-1},\ldots y^{\textnormal{local}}_{\ell d-1}$, which are known from the first round. For every $q\in[\ell-1]$, we send $z_{q}$ to reducerq+1. 3. 3.

Each reducerq+1 with $q\in[\ell-1]$ computes $y_{d(q+1)+j}=y^{\textnormal{local}}_{d(q+1)+j}+z_{q}$ for each $j\in[d]$.

We now describe the three rounds in more detail at the level of key-value pairs.

By defining the map function $\mu_{1}(\langle i;(\#S(x_{i}),i)\rangle{})=\langle i\div{}d;(\#S(x_{i}),i)\rangle{}$, each reducerq, for $q\in[\ell]$, receives $\#S(x_{dq}),\ldots,\#S(x_{d(q+1)-1})$ together with the correct indices. Thus we can compute in reducerq all local prefix-sums $y^{\textnormal{local}}_{dq},\ldots,y^{\textnormal{local}}_{d(q+1)-1}$ of these number. The output of reducerq consists of the local prefix-sums in the format $\langle q;(\textnormal{p-sum},q,j,y^{\textnormal{local}}_{q,j})\rangle$ for $j\in[d]$ and the last of each group of local prefix-sums in the format $\langle q;(\textnormal{last},y^{\textnormal{local}}_{d(q+1)-1})\rangle{}$, where $\textnormal{p-sum}=0$ and $\textnormal{last}=1$ is a simple binary identifier 2. 2.

By defining the map function $\mu_{2}(\langle q;(\textnormal{last},y^{\textnormal{local}}_{d(q+1)-1})\rangle{})=\langle 0;(\textnormal{last},y^{\textnormal{local}}_{d(q+1)-1})\rangle{}$, all last parts of the local prefix-sums can be gathered in reducer0*. Thus, the prefix-sums $z_{0},z_{1},\ldots z_{\ell-1}$ of $y^{\textnormal{local}}_{d-1},\ldots,y^{\textnormal{local}}_{d\ell-1}$ can be computed in it and the output of the reducer is $\langle 0;(\textnormal{last},i+1,z_{i})\rangle$ for every $i\in[\ell-1]$. All other key-value pairs—that is, those of the form $\langle q;(\textnormal{p-sum},q,j,y^{\textnormal{local}}_{q,j})\rangle$—are passed on unaltered.* 3. 3.

The input of the third round consists of the output pairs $\langle q;(\textnormal{p-sum},q,j,y^{\textnormal{local}}_{q,j})\rangle$ for all $j\in[d]$ and $q\in[\ell]$ passed on from the first round and the pairs $\langle 0;(\textnormal{last},q+1,z_{q})\rangle$ for all $q\in[\ell-1]$ from the second round. Defining the map function as $\mu_{3}(\langle q;(\textnormal{p-sum},q,j,y^{\textnormal{local}}_{q,j})\rangle{})=\langle q;(\textnormal{p-sum},q,j,y^{\textnormal{local}}_{q,j})\rangle$ and $\mu_{3}(\langle 0;(\textnormal{last},q+1,z_{q})\rangle{})=\langle q+1;(\textnormal{last},q+1,z_{q})\rangle{}$, we can, for each $j\in[d]$ and each $q\in\{1,\ldots,\ell-1\}$, compute $y_{q,j}=y^{\textnormal{local}}_{q,j}+z_{j}$ in reducerq.

The memory limitations of the mappers and reducers are clearly respected.

Lemma 3.10**.**

Each of the split values $\sigma_{1},\dots,\sigma_{\ell-1}$ can be computed in one reducer with the required prefix-sums being made available in one more $\mathcal{D}\mathcal{M}\mathcal{R}\hskip 1.00006pt\mathcal{C}$-round.

Proof 3.11**.**

If there is a $k\in[\ell-1]$ such that $y_{n-1}\leq kd$, then it is clear from the definition $\sigma_{q}=\max\{j\in[n]\mid y_{j}\leq qd\}$ of the split values that $\sigma_{k}=\sigma_{k+1}=\ldots=\sigma_{\ell-1}$. We can therefore assume that $y_{n-1}>(\ell-1)d$ and characterize, for each $q\in\{1,\dots,\ell-1\}$, the split value $\sigma_{q}$ as the unique integer satisfying $(q-1)d<y_{\sigma_{q}}\leq qd\text{ and }qd<y_{\sigma_{q}+1}$; see Figure 1.

This characterization is well defined since $0<\#S(x_{i})\leq\ell<d$ for each $i\in[n]$ and $y_{n-1}\leq d\ell\in O(N_{\textnormal{O}})$. For each $q\in[\ell]$, in order to determine the split value $\sigma_{q}$, it is therefore sufficient to have available in the respective reducer a sequence of consecutive prefix-sums such that the first one is at most $qd$ and the last one is greater than $qd$. This condition is satisfied if reducerq has the $d+2$ consecutive prefix-sums $y_{qd-1},y_{qd},\ldots,y_{(q+1)d-1},y_{(q+1)d}$ available. (For the first and the last reducer, the $d+1$ prefix-sums $y_{0},\ldots,y_{d-1},y_{d}$ and $y_{(\ell-1)d-1},y_{(\ell-1)d},\ldots,y_{\ell d-1}$, respectively, will suffice.) Slightly extending the sequence of available prefix-sums in each reducer by copying the overlapping prefix-sums from another reducer thus enables us to compute all split values in the $\ell$ reducers. Since for each $q\in[\ell]$, there are the $d$ prefix-sums $y_{qd},\ldots,y_{(q+1)d-1}$ in reducerq, each reducer can have the $d+2$ prefix-sums made available after one more round by having each neighboring reducer copy one more prefix-sum into it. We have $\sigma_{0}=-1$ and $\sigma_{\ell}=n-1$; it is thus immediately verified that, for every $q\in[\ell]$, the total number of subprograms in which input variables between $x_{\sigma_{q}+1}$ and $x_{\sigma_{(q+1)}}$ appear is at most $2d$, showing that all the memory restrictions on the reducers are observed.

Lemma 3.12**.**

Given $w$-PBP, $\alpha$, and the split values $\sigma_{0},\ldots,\sigma_{\ell}$, we can, for each $q\in[\ell]$, compute $\alpha_{q}$ in a constant number of $\mathcal{D}\mathcal{M}\mathcal{R}\hskip 1.00006pt\mathcal{C}$-rounds.

Proof 3.13**.**

We can assume that, for each $\kappa\in[\ell]$, the reducerκ has the subprogram $w$-PBP​κ, the $\kappa$th block of input assignments $\{(x_{j},v_{j})\mid\kappa\cdot d\leq j\leq(\kappa+1)d-1\}$, and the split values $\sigma_{0},\ldots,\sigma_{\ell}$ available. The output of reducerκ then consists of the following:

$\langle\kappa;(q,p,x_{i_{p}},f_{p},g_{p})\rangle{}$* for each line $(p,x_{i_{p}},f_{p},g_{p})$ in $w$-PBP​κ, where $\sigma_{q}+1\leq i_{p}\leq\sigma_{q+1}$.* 2. 2.

$\langle\kappa;(q,x_{j},v_{j})\rangle$* for each value assignment $(x_{j},v_{j})$ with $\sigma_{q}+1\leq j\leq\sigma_{q+1}$.*

For any $\kappa\in[\ell]$, we need to bound the total number of outputs with key $\kappa$ from above. From the definition of the split values we see that this number is in $O(d)$ since it is bounded by the number of lines, which is at most $2d$, plus the number of assignments, which is at most $d$.

Naturally, the map function $\mu$ of the next round is defined by

$\mu(\langle\kappa;(q,p,x_{j_{p}},f_{p},g_{p})\rangle{})=\langle q;(p,x_{j_{p}},f_{p},g_{p})\rangle{}$* and* 2. 2.

$\mu(\langle\kappa;(q,x_{j},v_{j})\rangle{})=\langle q;(x_{j},v_{j})\rangle{}$.

For any $\kappa\in[\ell]$, the assignment variables $\alpha_{q}$ can be computed by the subsequent reduce function using the key-value pairs produced above. For each $q\in[\ell]$, the reducerq has now available the lines of $w$-PBP and the value assignments for the input variables between $x_{\sigma_{q}+1}$ and $x_{\sigma_{q+1}}$. It can therefore go through all the program lines and determine, on the one hand, which value assignments they require and, on the other hand, to which subprogram they belong. To required assignment information is then sent to the respective reducers by outputting $\langle q;(p\div{}d,p,x_{i_{p}},v_{i_{p}})\rangle{}$.

We finally obtain the desired inclusion by applying Theorem 3.3 and Lemmas 3.4 through 3.12.

Theorem 3.14**.**

We have $\mathcal{N}\mathcal{C}^{1}\subseteq\mathcal{D}\mathcal{M}\mathcal{R}\hskip 1.00006pt\mathcal{C}^{0}$.

3.3 Simulating $\mathcal{N}\mathcal{C}^{i}$ For All $i\geq 2$

For the higher levels in the hierarchy of Nick’s class, we show how to simulate the involved circuits directly. We begin with a short outline of the proof.

Let $C_{n}=(V_{n},E_{n})$ be a $\mathcal{N}\mathcal{C}^{i+1}$ circuit with an input of size $n$, given as a set of nodes and a set of directed edges, together with an input assignment $\alpha$. The total size of $C_{n}$ in bits is $N_{\textnormal{O}}$, the total size of the input assignment in bits is $N_{\textnormal{I}}$, and $N=N_{\textnormal{O}}+N_{\textnormal{I}}$. Note that $\textnormal{size}(C_{n})$ is polynomial in $n$ and $0pt(C_{n})\in O(\log^{i}n)$. We will take the following steps to simulate the circuit $C_{n}$ with deterministic MapReduce computations:

We compute the level of each node in $C_{n}$. 2. 2.

The nodes and edges are sorted by their level. 3. 3.

Both the circuit $C_{n}$ and the input assignment $\alpha$ are divided equally among the reducers. 4. 4.

We split the circuit into subcircuits computable in a constant number of rounds. 5. 5.

A custom communication scheme collects and constructs the complete subcircuits. 6. 6.

The entire circuit is evaluated via evaluation of the subcircuits.

Note that equal division of $C_{n}$ in the third step is very different from the split in the forth one, where the parts may differ radically in size. Great care must be taken so as to no violate any of the memory and time restrictions, necessitating two unlike partitions. The subsequent steps then need to mediate between these dissimilar divisions. We will show that the steps $(1)$ to $(6)$ can be computed in $O(\log n)$, $O(1)$, $O(1)$, $O(1)$, $O(\log n)$ and $O(0pt(C_{n})/\log n)$ rounds, respectively, yielding the desired theorem.

Theorem 3.15**.**

We have $\mathcal{N}\mathcal{C}^{i+1}\subseteq\mathcal{D}\mathcal{M}\mathcal{R}\hskip 1.00006pt\mathcal{C}^{i}$, for all $i\in\mathbb{N}_{+}$ and all $0<\varepsilon<1/2$.

3.3.1 Computing The Levels

We begin by showing how to compute the level of each node in the circuit in $O(\log n)$ $\mathcal{D}\mathcal{M}\mathcal{R}\hskip 1.00006pt\mathcal{C}$-rounds by simulating a CRCW-PRAM algorithm. (We mention in passing that this step requires more than a constant number of rounds, which prevents us from obtaining the result for $\mathcal{N}\mathcal{C}^{1}\subseteq\mathcal{D}\mathcal{M}\mathcal{R}\hskip 1.00006pt\mathcal{C}^{0}$ by simulating the circuits directly; the separate approach from Subsection 3.2 via Barrington’s theorem is thus required for this case.)

In [18], an algorithm is presented that computes the levels of all nodes in a directed acyclic graph can on a CREW-PRAM with $O(n+m)$ processors in $O(\log^{2}m)$ time, where $n$ and $m$ are the numbers of nodes and edges in the graph, respectively. The first stage of this algorithm relies partly on the computation of prefix-sums, which can be computed much more efficiently when switching to a CRCW-PRAM, as we will show below. A straightforward adaptation of the analysis in [18], taking into account the maximum in-degree and out-degree and separating out the computation of prefix-sums, yields the following result.

Lemma 3.16**.**

Let $G=(V,E)$ be a directed acyclic graph with $n$ nodes, $m$ edges, maximum in-degree $d_{\textnormal{in}}$, and maximum out-degree $d_{\textnormal{out}}$. The level of each node in $G$ can then be computed on a CRCW-PRAM with $P\in O(m+P_{\textnormal{P-Sum}}(O(m)))$ processors and time $T\in O((\log m)\cdot(T_{\textnormal{P-Sum}}(O(m))+\log\max\{d_{\textnormal{in}},d_{\textnormal{out}}\}))$, where $P_{\textnormal{P-Sum}}(q)$ and $T_{\textnormal{P-Sum}}(q)$ denote, respectively, the number of processors and the computation time to compute the prefix-sums of $q$ numbers on a CRCW-PRAM.

In the following lemma, we aim to lower the time and memory requirements for computing prefix-sums on a CRCW-PRAM as far as possible.

Lemma 3.17**.**

The prefix-sums of $q$ numbers can be computed on a CRCW-PRAM with $P\in O(q\log q)$ processors and memory $M\in O(q)$ in constant time.

Proof 3.18**.**

We use a Sum-CRCW-PRAM, where concurrent writes to the same memory register are resolved by adding up all simultaneously assigned numbers. [10]. Let $q$ numbers $x_{0},x_{1},\ldots,x_{q-1}$ be given as input. Without loss of generality, we assume $q$ to be a power of $2$ and calculate $s_{i}(j)=\sum_{j2^{i}\leq p<(j+1)2^{i}}x_{p}$ for all $i\in[1+\log q]$ and all $j\in[q/2^{i}+1]$; see Figure 2 for an illustrating example.

Since each of the $q/2^{i}$ elements in $s_{i}$ is the sum of $2^{i}$ elements, we can—by allocating $q$ processors for each $i\in[1+\log q]$—compute every $s_{i}(j)$ in a Sum-CRCW-PRAM with $O(q\log q)$ processors and $O(1)$ time.

We now describe how the prefix-sums $y(0),y(1),\ldots,y(q-1)$ are computed from the $s_{i}(j)$. Assume first that $j+1$ is a power of $2$, that is, $j+1=2^{p}$. Then we have $y(j)=s_{p}(0)$, so the value has already been computed. If $j+1=2^{p}+1$ for some $p$, then we have $y(j)=s_{p}(0)+s_{0}(2^{p})$, so we need to add two summands. In general, $y(j)$ can be calculated as the sum of at most $\log q-1$ known summands.

Let $a_{\log q}^{j}a_{(\log q)-1}^{j}\ldots a_{0}^{j}$ be the binary representation of $j+1$. Now, we can see that

[TABLE]

that is, $y(j)$ can be computed as the sum of all $s_{p}((j+1-2^{p})\div{}2^{p})$ such that $a_{p}^{j}=1$. Thus, it is sufficient to supply a maximum of $(\log q)-1$ processors for the calculation of each $y(j)$ in a second time step, and the prefix-sums can be computed on a Sum-CRCW-PRAM with $O(q\log q)$ processors in constant time.

We plug in the result of Lemma 3.17 into Lemma 3.16 and then apply it to the graph $C_{n}$. Since its in-degrees and out-degrees are bounded by a constant $\Delta$, we have $m\leq\Delta n/2\in O(n)$. Hence we can compute the levels of the nodes of $C_{n}$ on a CRCW-PRAM with $P\in O(N\log N)$ processors in time $T\in O(\log n)$. By Corollary 3.2, we obtain the following result.

Lemma 3.19**.**

Computing the levels of all nodes in $C_{n}$ is in $\mathcal{D}\mathcal{M}\mathcal{R}\hskip 1.00006pt\mathcal{C}^{1}$.

Proof 3.20**.**

From Lemmas 3.16 and 3.17 we know that the level of each node in $C_{n}$ can be computed in $T\in O(\log n)$ time on a Sum-CRCW-PRAM with $P\in O(N+N\log N)$ processors. Now, Corollary 3.2 yields a MapReduce simulation of this Sum-CRCW-PRAM. We need to check that the conditions of Corollary 3.2 are indeed all satisfied: From $T\in O(\log n)$, $P\in O(N+N\log N)$, and $M\in O(N)$ follows $M+P\in O(N\log N)$ and $\log_{N^{1-\varepsilon}}(M+P)\in O(1)$, hence we have $(M+P)\log_{N^{1-\varepsilon}}(M+P)\in O(N^{2(1-\varepsilon)})$. Thus, the level of each node in $C_{n}$ can be computed in $O(\log n)$ $\mathcal{D}\mathcal{M}\mathcal{R}\hskip 1.00006pt\mathcal{C}$-rounds.

3.3.2 Sorting By Levels

Once the levels of all nodes are computed, each node in the circuit can be represented as $(\textnormal{level}(x_{i}),x_{i})$. Recall that the depth of $C_{n}$ is just the maximum level. Since $0pt(C_{n})\in O(\log^{k}n)$ for some $k\in\mathbb{N}_{+}$ and the number of nodes is bounded by the number of edges $\textnormal{size}(C_{n})\in O(N)$, we can encode each pair $(\textnormal{level}(x_{i}),x_{i})$ by appending to a bit string of length $\log(c_{1}\log^{k}n)$ another one of $\log(c_{2}N)=\log(cN\log^{k}n)$, for appropriate constants $c_{1}$ and $c_{2}$, which results in a bit string of length $\lg(cN\log^{k}n)$ for $c=c_{1}c_{2}\in\mathbb{N}$. This enables us to identify each pair $(\textnormal{level}(x_{i}),x_{i})$ with a different bit string, which can interpreted as an integer bounded by $cN\log^{k}n$. We call this integer the sorting index of node $x_{i}$. Crucially, we chose the bit string to start with the encoding of the level. Sorting the sorting indices thus means to sort the nodes of $C_{n}$ by their level. The following lemma shows how prefix-sums can be used to perform such a sort so efficiently on a CRCW-PRAM that we can apply Corollary 3.2 to simulate it in a constant number of $\mathcal{D}\mathcal{M}\mathcal{R}\hskip 1.00006pt\mathcal{C}$-rounds.

Lemma 3.21**.**

A CRCW-PRAM with $P\in O(D\log D)$ processors and memory $M\in O(D)$ can sort any subset $I\subseteq\{1,\dots,D\}$ of integers in constant time.

Proof 3.22**.**

Recall that we use a Sum-CRCW-PRAM that sums up concurrent writes. Assume that the input and output are stored in the arrays $x[0],\ldots,x[p-1]$ and $y[0],\ldots,y[p-1]$, respectively. We will use two auxiliary arrays $z[0],\ldots,z[D]$ and $\hat{z}[0],\ldots,\hat{z}[D]$ of size $D+1$. The algorithm works in for steps:

Initialize $z$ by using $D+1\leq P$ processors to set $z[k]\leftarrow 0$ for all $k\in[D+1]$. 2. 2.

Use $p\leq P$ processors in parallel to set $z[x[k]]\leftarrow 1$ for all $k\in[p]$. 3. 3.

Compute the prefix-sums of the array $z$ and save them into $\hat{z}$. 4. 4.

Use $D$ processors to set, for all $k\in\{1,\dots,D\}$ in parallel, $y[\hat{z}[k]]\leftarrow k$ if and only if $\hat{z}[k]\neq\hat{z}[k-1]$.

Since the prefix-sums of $D$ numbers can be computed by the Sum-CRCW PRAM with $P\in O(D\log D)$ processors and memory $M\in O(D)$ in constant time by Lemma 3.17, the above algorithm stays within these bounds as well.

We now prove that this algorithm is correct. First we observe that after step 2, for every $k\in\{1,\dots,D\}$, we have $z[k]=1$ if and only if one of the $p$ integers to be sorted is $k$. Because $\hat{z}$ contains the prefix-sums of $z$, the value stored in $\hat{z}[k]$ hence tells us how many of the $p$ integers in $x$ are at most $k$. (Note that accordingly we always have $z[0]=\hat{z}[0]=0$.) Thus $k$ is one of the integers in $x$ if and only if $\hat{z}[k]=\hat{z}[k-1]+1$; otherwise, we have $\hat{z}[k]=\hat{z}[k-1]$. As a consequence, the array $\hat{z}$ contains exactly the indices of $x$, namely $[p]$, as values in non-decreasing order, that is, $0=\hat{z}[0]\leq\hat{z}[1]\leq\dots\leq\hat{z}[D-1]\leq\hat{z}[D]=p$. Stepping through $\hat{z}$ from start to end, that is, from $k=0$ to $k=D$, we therefore observe an increment of 1 from $\hat{z}[k-1]$ to $\hat{z}[k]$ exactly if $k$ one of the integers to be sorted. This means that in step 4 the integers contained in $x$ are detected from left to right in ascending order and subsequently stored into $y$ in the same order.

Combining Lemma 3.21 and Corollary 3.2 we obtain, by a careful analysis using $\varepsilon\neq 1/2$, the promised result.

Corollary 3.23**.**

Let $c\in\mathbb{N}$ and $0<\varepsilon<1/2$. Any set of distinct integers from $\{1,\dots,\lceil cN\log^{k}n\rceil\}$ can be sorted in a constant number of $\mathcal{D}\mathcal{M}\mathcal{R}\hskip 1.00006pt\mathcal{C}$-rounds.

Proof 3.24**.**

We apply Lemma 3.21 with $D\in O(N\log^{k}n)$. We have $D\in O(N\log^{k}N)\subseteq O(N^{1+\zeta})$ and thus also $D\log D\in O(N^{1+\zeta})$ for any constant $\zeta>0$. Choose any $\zeta<1-2\varepsilon$, which is possible for $\varepsilon<1/2$. The sorting is then possible on a CRCW-PRAM with $O(N^{1+\zeta})$ processors and $O(N^{1+\zeta})$ memory in constant time. By Corollary 3.2, this CRCW-PRAM can be simulated in a constant number of $\mathcal{D}\mathcal{M}\mathcal{R}\hskip 1.00006pt\mathcal{C}$-rounds because $\log_{N^{1-\varepsilon}}(N^{1+\zeta})=(1+\zeta)/(1-\varepsilon)\in O(1)$ and $O(N^{1+\zeta})\subseteq O(N^{2(1-\varepsilon)})$.

Once all the nodes are sorted by their sorting index (and therefore implicitly by their level), we can enumerate them in ascending order using a sorting index $j$; that is, we store each node as the key-value pair $\langle j;(\textnormal{level}(v),v)\rangle{}$. Clearly, we obtain an analogous representation of the edges in the form $\langle i;((j,(\textnormal{level}(v),v),(j^{\prime},(\textnormal{level}(v^{\prime}),v^{\prime}))\rangle{}$, which will prove useful later on.

3.3.3 Division of Circuit And Assignment Among Reducers

As we have already seen when discussing the branching programs, an assignment $\alpha$ to input variables $\mathcal{X}=\{x_{0},x_{1},\ldots,x_{n-1}\}$ can be represented as a set $\{\langle i;(x_{i},v_{i})\rangle\mid i\in[n]\}$ of key-value pairs, where $\alpha(x_{i})=v_{i}\in\{0,1\}$.

The circuit $C_{n}$ is now divided into $\ell=N_{\textnormal{O}}^{\varepsilon}$ subsets of edges according to the sorting indices and input values that are assigned to each subset as in the case of branching programs. For every $q\in[\ell]$, let $C_{n}^{q}=\{((j,\textnormal{level}(v),v),(j^{\prime},\textnormal{level}(v^{\prime}),v^{\prime}))\mid qd\leq j\leq(q+1)d-1\}$, where $d=N_{\textnormal{O}}^{1-\varepsilon}$, be the $q$th subset. Note that $|C_{n}^{q}|\in O(d)$. For every $q\in[\ell]$, the set of variables appearing in $C_{n}^{q}$ is denoted as $\mathcal{X}_{q}$ and the assignment $\alpha_{q}$ to $\mathcal{X}_{q}$ is represented as $\{\langle j;x_{q,j},v_{q,j}\rangle\mid j\in[|\alpha_{q}|]\}$, where $x_{q,j}$ is the $j$th variable that appears as an input in $C_{n}^{q}$, and $v_{q,j}$ is its assignment value. Just as seen in Lemma 3.12 for the case of a branching program, we can now compute $\alpha_{q}$ from $C_{n}$ and $\alpha$ for all $q\in[\ell]$, yielding the following lemma.

Lemma 3.25**.**

Computing $\alpha_{q}$ from $C_{n}$ and $\alpha$ is in $\mathcal{D}\mathcal{M}\mathcal{R}\hskip 1.00006pt\mathcal{C}^{0}$ for every $q\in[\ell]$.

We can therefore assume that each input node is represented by $\langle j;(\textnormal{level}(x_{j_{i}}),x_{j_{i}},v_{j_{i}})\rangle$, a key-value pair that is computed from $C_{n}^{q}$ and $\alpha_{q}$ for $q\in[\ell]$ in a single $\mathcal{D}\mathcal{M}\mathcal{R}\hskip 1.00006pt\mathcal{C}$-round.

3.3.4 Division Into Subcircuits By Levels

We divide $C_{n}=(V_{n},E_{n})$ into as few subcircuits as possible such that the simulation of each subcircuit is in $\mathcal{D}\mathcal{M}\mathcal{R}\hskip 1.00006pt\mathcal{C}^{0}$ and we can evaluate $C_{n}$ by evaluating the subcircuits sequentially.

Given $v\in V_{n}$ and $\delta\in\mathbb{N}$, we define the $v$-down-circuit $C_{\delta}^{\textnormal{down}}(v)=(V_{\delta}^{\textnormal{down}}(v),E_{\delta}^{\textnormal{down}}(v))$ of depth $\delta$ to be the subcircuit of $C_{n}$ induced by $V_{\delta}^{\textnormal{down}}(v)=\{u\mid\textnormal{level}(v)\leq\textnormal{level}(u)\leq\textnormal{level}(v)+\delta,u\rightarrow^{*}v\}$, where $u\rightarrow^{*}v$ means that there is a directed path of any length (including [math]) from $u$ to $v$ in $C_{n}$. The $v$-up-circuit $C_{\delta}^{\textnormal{up}}(v)=(V_{\delta}^{\textnormal{up}}(v),E_{\delta}^{\textnormal{up}}(v))$ of depth $\delta$ is analogously the subcircuit of $C_{n}$ induced by $V_{\delta}^{\textnormal{up}}(v)=\{u\mid\textnormal{level}(v)-\delta\leq\textnormal{level}(u)\leq\textnormal{level}(v),v\rightarrow^{*}u\}$.

When dividing $C_{n}$ into subcircuits we have two conflicting goals. On the one hand, we want as few of them as possible, which implies that they have to be of great depth. On the other hand, we need to simulate them in MapReduce without exceeding the memory bounds. A depth in $O(\log n)$ turns out to be the right choice. Let $s=\gamma(\log n)/\log\Delta$, where $\Delta\geq 2$ is a constant bounding the maximum degree of $C_{n}$ and $\gamma$ is an arbitrary constant satisfying $0<\gamma<1-2\varepsilon$. (Note that such a $\gamma$ exists exactly if $\varepsilon<1/2$.) Since a tree of depth $s$ and maximum degree bounded by a constant $\Delta$ contains at most $\sum_{i=1}^{s}\Delta^{i}$ edges, their size is in $O(\Delta^{s})=O(n^{\gamma})\subseteq O(N^{\gamma})$. Hence each reducer may contain up to $N^{1-\varepsilon}/N^{\gamma}$ such subcircuits without exceeding the memory constraint of $O(N^{1-\varepsilon})$; see Figure 3. We denote this number of allowed subcircuits per reducer by $\beta=N^{1-\varepsilon-\gamma}$.

For each $i\in[\lceil 0pt(C_{n})/s\rceil+1]$, we define $L_{i}=i\cdot s$. For every node $v$ on level $L_{i}$—that is, with $\textnormal{level}(v)=L_{i}$—we call the $v$-down-circuit ($v$-up-circuit, resp.) of depth $s$ a $L_{i}$-down-circuit ($L_{i}$-up-circuit, resp.). We will construct in each reducer the $v$-down-circuits and $v$-up-circuits of depth $1$ of all its nodes. From those we then construct all $L_{i}$-down-circuits and $L_{i}$-up-circuits for every $i$. Note that we can evaluate all $L_{i}$-down-circuits if the values of the nodes of level $L_{i+1}$ are given. The values of the nodes $v$ of level $L_{i+1}$ that are necessary to compute the $L_{i}$-up-circuits are then known from the $L_{i+1}$-down-circuits.

When the circuit $C_{n}$ is divided into $L_{i}$-down-circuits, there may exist edges of $C_{n}$ that are not contained in any $L_{i}$-down-circuit. If an edge $((j_{u},\textnormal{level}(u),u),(j_{v},\textnormal{level}(v),v))$ satisfies $L_{i_{u}}\leq\textnormal{level}(u)\leq L_{i_{u}+1}$ and $L_{i_{v}}\leq\textnormal{level}(v)\leq L_{i_{v}+1}$ for $i_{u}\neq i_{v}$, then this edge is not included in any $L_{i_{u}}$-down-circuit nor any $L_{i_{v}}$-down-circuit. We call such edges level-jumping edges; see Figure 4 for an example. We would like to replace every level-jumping edge $(u,v)$ by a path from $u$ to $v$ that consists only of edges that will be part of the respective $L_{i}$-down-circuits and $L_{i}$-up-circuits in the resulting, augmented circuit. The following lemma states that this is possible without increasing the size by too much.

Lemma 3.26**.**

We can subdivide the jumping edges in $C_{n}$ in a way that renders the subcircuit-wise evaluation possible without increasing the size beyond $O(N)$.

Proof 3.27**.**

Let $((j_{u},\textnormal{level}(u),u),(j_{v},\textnormal{level}(v),v))$ be a jumping edge, where $L_{i_{u}}\leq\textnormal{level}(u)\leq L_{i_{u}+1}$, $L_{i_{v}}\leq\textnormal{level}(v)\leq L_{i_{v}+1}$ and $i_{u}<i_{v}$. If $i_{u}=i_{v}-1$, then this edge is divided into two edges $((j_{u},\textnormal{level}(u),u),\textnormal{dummy})$ and $(\textnormal{dummy},(j_{v},\textnormal{level}(v),v))$, introducing a new node dummy of the id kind with $\textnormal{level}(\textnormal{dummy})=i_{v}$. If $i_{u}\leq i_{v}-2$, then this edge is divided into three edges $((j_{u},\textnormal{level}(u),u),\textnormal{dummy}_{1})$, $(\textnormal{dummy}_{1},\textnormal{dummy}_{2})$ and $(\textnormal{dummy}_{2},(j_{v},\textnormal{level}(v),v))$, introducing two new nodes with $\textnormal{level}(\textnormal{dummy}_{1})=i_{u}+1$, $\textnormal{level}(\textnormal{dummy}_{2})=i_{v}$. Having divided the jumping edges in this way, the newly created edges are all part of some dummy-down-circuit or dummy-up-circuit, except for edges of the form $(\textnormal{dummy}_{1},\textnormal{dummy}_{2})$. Note that we cannot further subdivide the edges of the form $(\textnormal{dummy}_{1},\textnormal{dummy}_{2})$ because we would exceed the size limit on the circuit otherwise. The most convenient way to deal with this is to adjust our definition of down-circuits and up-circuits such that every edge of the form $(\textnormal{dummy}_{1},\textnormal{dummy}_{2})$ is considered to be both a $\textnormal{dummy}_{1}$-down-circuit and a $\textnormal{dummy}_{2}$-up-circuit on its own. This way, every edge in the augmented circuit is included in some down-circuit or up-circuit. Note that this augmentation can be performed in a single round and that the size of the augmented circuit is in $O(N)$. In what follows, we consider $C_{n}$ to be this augmented circuit.

3.3.5 Construction of Subcircuits in Reducers

Having described the subcircuits on which the evaluation of the entire circuits will be based we now need to show how to split and construct them in the $\ell$ different reducers. In each reducer, We start with the nodes $v$ contained in it that satisfy $\textnormal{level}(v)=L_{i}$ for any $i$ and the associated $v$-down-circuits and $v$-up-circuits of depth 1. We then iteratively increase the depth one by one, until the full $L_{i}$-down-circuits and $L_{i}$-up-circuits of depth up to $s$ are constructed. Note that the nodes of any level $L_{i}$ and their corresponding circuits may scattered across multiple reducers since edges were split equally among them according to their the sorting index and not depending on the level. We therefore need to carefully implement a communication scheme that allows each reducer to encode requests for missing edges required in the construction, which are then delivered to them in multiple rounds, without exceeding any of the memory or time bounds. Taking care of all these details, we obtain the following lemma.

Lemma 3.28**.**

Given $C_{n}$, all $L_{i}$-down-circuits and $L_{i}$-up-circuits can be constructed in $O(\log n)$ $\mathcal{D}\mathcal{M}\mathcal{R}\hskip 1.00006pt\mathcal{C}$-rounds whenever $0<\varepsilon<1/2$.

Proof 3.29**.**

In the first round, the map function $\mu_{1}$ is defined such that each reducerq is assigned (via the choice of the key) $\beta$ nodes of the form $\langle j;(\textnormal{level}(v),v)\rangle{}$ and directed edges adjacent to these nodes. Note that one edge can thus be assigned to two different reducers, once as an outgoing, once as in in-going edge. Specifically, we define

[TABLE]

for the key-value pairs representing nodes and

[TABLE]

for the key-value pairs representing edges.

In the subsequent execution of $\rho_{1}$, each reducer can therefore directly construct the $v$-up-circuits and $v$-down-circuits of depth $1$ for its $\beta$ assigned nodes. We will now describe how some of these initial circuits, namely those on levels $L_{i}$ for any $i\in[r]$, can be used to extended to full $L_{i}$-up-circuits and $L_{i}$-down-circuits by iteratively increasing the circuit depth one by one in the following way:

Let $v$ be a node with $\textnormal{level}(v)=L_{i}$ in reducerq for any $i\in[r]$ and $q\in[\ell]$. We want to extend $C_{1}^{\textnormal{down}}(v)$ and $C_{1}^{\textnormal{up}}(v)$ to $C_{2}^{\textnormal{down}}(v)$ and $C_{2}^{\textnormal{up}}(v)$, respectively. Let $u_{\textnormal{in}}$ ($u_{\textnormal{out}}$, resp.) be any node of in-degree (out-degree, resp.) [math] in it, that is, any node that potentially needs to be extended by one or multiple edges. These extending edges are not necessarily available in reducerq, however. We need to find out which reducer stores them—if there are any—and then request these edges from it in some way. To determine the right reducer, we make use of the sorting index stored alongside each node, even when part of an edge. Any edge $(u_{\textnormal{in}},v)$ that we need to check for possible extensions is in fact represented as $\langle q\;,\;(\,(j_{u_{\textnormal{in}}},\textnormal{level}(u_{\textnormal{in}}),u_{\textnormal{in}})\,,\,(j_{v},\textnormal{level}(v),v)\,)\;\rangle$ in reducerq. The number of the reducer containing the downward extending edges is now retrieved as $\textnormal{to}(u_{\textnormal{in}})=j_{u_{\textnormal{in}}}\div\beta$. Analogously, the upward extending edges for an edge $(v,u_{\textnormal{out}})$ are to be found in reducer${}_{\textnormal{to}}(u_{\textnormal{out}})$, where $To(u_{\textnormal{out}})=j_{u_{\textnormal{out}}}\div\beta$. We now know whom to ask for edges extending the subcircuit beyond node $u$, namely reducer number $\textnormal{to}(u)$. Let $\textnormal{from}(v)=q$ denote the number of the reducer sending the request, which we encode in form of the key-value pair $\langle q;(u,\textnormal{to}(u),\textnormal{from}(v))\rangle$.

Each reducerq does the above for every node with possible extending edges and also passes along to the mapper all $v$-up-circuits and $v$-down-circuits constructed so far unaltered. This concludes the first round.

In the second round, the map function $\mu_{2}$ naturally re-assigns $\langle q;(u,\textnormal{to}(u),\textnormal{from}(v))\rangle$ to reducer${}_{\textnormal{to}(u)}$, and returns the $v$-up-circuits and $v$-down-circuits to the reducers that sent them. Having received the edge request of the form of $\langle\textnormal{to}(u);(u,\textnormal{to}(u),\textnormal{from}(v))\rangle$ while executing $\rho_{2}$ reducer${}_{\textnormal{to}(u)}$ now sends all edges potentially useful to reducer${}_{\textnormal{from}(v)}$—that is, the entire $u$-up-circuit and the entire $u$-down-circuit of depth $1$—to the next mapper in the form of a pair $(\textnormal{from}(v),e)$ for every edge containing node $u$. As before, all other circuits constructed so far get passed along without modification as well.

In the third round, the map function $\mu_{3}$ routes the requested edges to the requesting reducer by generating the key-value pairs $\langle\textnormal{from}(v);(\textnormal{from}(v),e\rangle{}$. In the reducing step, which implements the same reduce function $\rho_{1}$ as in the first round, reducer reducer${}_{\textnormal{from}(v)}$ now finally has all fully extend the $v$-up-circuits and $v$-down-circuits to depth 2.

Since performing the two rounds $\mu_{2},\rho_{2},\mu_{3},\rho_{1}$ deepens the $L_{i}$-up-circuits and $L_{i}$-down-circuits by one level in the way just seen, the complete $L_{i}$-up-circuits and $L_{i}$-down-circuits can be constructed by repeating these two rounds $s$ times.

It is again clear that the memory and I/O requirements of the reducers are all met in every round since the input size and output size are in $O(d)$ for each reducer. Moreover,the total memory for storing the $v$-up-circuits and $v$-down-circuits is $\beta\cdot N\in O(N^{1+\gamma})$ because $C_{n}$ has at most $N_{\textnormal{O}}\in O(N)$ nodes. Since the constant $\gamma$ was chosen such that $0<\gamma\leq 1-2\varepsilon$, we have $N^{1+\gamma}\in O(N^{2(1-\varepsilon)})$ and thus all up-circuits and down-circuits can be stored in the respective reducers.

3.3.6 Evaluation Via Subcircuits

The main idea in the proof of the following lemma is to compute the evaluation values subcircuit-wise, starting with the deepest ones, and then iteratively moving up the circuit in $0pt(C_{n})/s$ rounds, passing on the newly computed values to the right reducers, until the value of the unique output node is known.

Lemma 3.30**.**

If all up-circuits and down-circuits are constructed in the proper reducers, $C_{n}$ can be evaluated in $O(0pt(C_{n})/\log n)$ $\mathcal{D}\mathcal{M}\mathcal{R}\hskip 1.00006pt\mathcal{C}$-rounds.

Proof 3.31**.**

Without loss of generality, let $0pt(C_{n})$ be divisible by $s$ and let $r=0pt(C_{n})/s$. Once all $L_{i}$-down-circuits and $L_{i}$-up-circuits for all $i\in\{1,\ldots,r\}$ have been constructed, we can evaluate $C_{n}$ on the given input assignment. We begin by evaluating the $L_{r-1}$-down-circuits. Since every input node has its value assigned in a $v$-down-circuit, the $L_{r-1}$-down-circuits can be computed in the reducers containing these $v$-down-circuits. With the values of all nodes at level $L_{r-1}$ determined, we can send the necessary values to the $L_{r-2}$-down-circuits and, in the case of edges that were divided using two dummy nodes, to lower-level down-circuits. Nodes at level $L_{r-1}$ that are necessary to compute $L_{r-2}$-down-circuits are described in the $L_{r-1}$-up-circuits. Any node $v$ at level $L_{r-1}$ that is necessary to compute $L_{r-2}$-down-circuits is described in the $v$-up-circuit. Therefore, the output of the reducerq is as follows: Let $v$ be at level $L_{r-1}$ and let $u_{i}$, for $i\in\{1,\ldots,k_{v}\}$, be the nodes at level $L_{r-2}$ in the $v$-up-circuit. For each $v$ in reducerq, it outputs $(\textnormal{to}(u_{i}),v,\textnormal{val}(v))$, where $\textnormal{to}(u_{i})$ is the index of the reducer containing the $u_{i}$-down-circuit and $\textnormal{val}(v)$ is the value of $v$ determined in the computation of $v$-down-circuit. The reducerq also passes on all $v$-down-circuits and $v$-up-circuits contained in it.

In the next round, the map function sends each $(\textnormal{to}(u_{\textnormal{in}}),v,\textnormal{val}(v))$ to the reducer containing the $u_{\textnormal{in}}$-down-circuit; that is, it generates the key-value pair $\langle\textnormal{to}(u_{\textnormal{in}});(v,\textnormal{val}(v))\rangle$. Of course, the map function also passes along all $v$-down-circuits and $v$-up-circuits to the proper reducers.

Since now each $L_{r-2}$-down-circuit is contained completely in a reducer that has gathered all values of nodes at level $L_{r-1}$ necessary to compute this subcircuit, all $L_{r-2}$-down-circuits can be computed in their reducers. Now we can compute the values of nodes higher and higher up in the circuit, by iterating the last mapping-reducing function pair, until the value is finally known for the unique output node.

As before, we clearly stay within the memory and I/O buffer limits of each reducer.

4 Conclusion and Research Opportunities

In a substantial improvement over all previously known results, we have shown that $\mathcal{N}\mathcal{C}^{i+1}\subseteq\mathcal{D}\mathcal{M}\mathcal{R}\hskip 1.00006pt\mathcal{C}^{i}$ for all $i\in\mathbb{N}$. In the case of $\mathcal{N}\mathcal{C}^{1}\subseteq\mathcal{D}\mathcal{M}\mathcal{R}\hskip 1.00006pt\mathcal{C}^{0}$, we have proved this result for every feasible choice of $\varepsilon$ in the model, that is, for $0<\varepsilon\leq 1/2$. For $i>0$, we have shown the result to hold for all but one value, namely $\varepsilon=1/2$.

Achieving these two results required a detailed description of two different, delicate simulations within the MapReduce framework. For the case of $\mathcal{N}\mathcal{C}^{1}$, which is particularly relevant in practice, we applied Barrington’s theorem and simulated width-bounded branching programs [2], whereas we directly simulated the circuits for the higher levels of the hierarchy. We emphasize that none of the two approaches can replace the other: Barrington’s theorem only gives a characterization for the first level of the $\mathcal{N}\mathcal{C}$ hierarchy and the second approach does not even yield $\mathcal{N}\mathcal{C}^{1}\subseteq\mathcal{M}\mathcal{R}\hskip 1.19995pt\mathcal{C}^{0}$. (Recall that $\mathcal{D}\mathcal{M}\mathcal{R}\hskip 1.00006pt\mathcal{C}$ is just the deterministic variant of $\mathcal{M}\mathcal{R}\hskip 1.19995pt\mathcal{C}$, so we have $\mathcal{D}\mathcal{M}\mathcal{R}\hskip 1.00006pt\mathcal{C}^{i}\subseteq\mathcal{M}\mathcal{R}\hskip 1.19995pt\mathcal{C}^{i}$ for all $i\in\mathbb{N}$.)

We would like to briefly address the small question that immediately arises from our result, namely whether it is possible to extend the inclusion $\mathcal{N}\mathcal{C}^{i+1}\subseteq\mathcal{D}\mathcal{M}\mathcal{R}\hskip 1.00006pt\mathcal{C}^{i}$ of Theorem 3.15 to the case $\varepsilon=1/2$. Going through all involved lemmas, we see that the two reasons that our proof does not work in this corner case are the sorting of the nodes using Lemma 3.23 and the construction of the up-circuits and down-circuits in Lemma 3.28. Regarding the former, we can avoid the restriction by allowing randomization. For the latter, it is not clear that this can be achieved, however. If there was any way to construct the levels for $\varepsilon=1/2$ as well, then Theorem 3.15 would immediately extend to the full range $0<\varepsilon\leq 1/2$ of feasible choices for $\varepsilon$.

Besides dealing with the small issue mentioned above, the natural next step for future research is to take the complementary approach and address the reverse relationship: Having shown in this paper how to obtain efficient deterministic MapReduce algorithms for parallelizable problems, we now aim to include the largest possible subset of $\mathcal{D}\mathcal{M}\mathcal{R}\hskip 1.00006pt\mathcal{C}^{i}$ into $\mathcal{N}\mathcal{C}^{i+1}$ for all $i\in\mathbb{N}$. By simply padding a $\mathcal{P}$-complete language so as to include it in $\mathcal{D}\mathcal{M}\mathcal{R}\hskip 1.00006pt\mathcal{C}^{0}$, Karloff et al. [11, Thm. 4.1] proved that $\mathcal{D}\mathcal{M}\mathcal{R}\hskip 1.00006pt\mathcal{C}^{0}\subseteq\mathcal{N}\mathcal{C}$ would imply $\mathcal{P}=\mathcal{N}\mathcal{C}$, an equality generally deemed unlikely to hold. Thus we cannot expect to prove $\mathcal{D}\mathcal{M}\mathcal{R}\hskip 1.00006pt\mathcal{C}^{i}=\mathcal{N}\mathcal{C}^{i+1}$, but try to determine $\mathcal{D}\mathcal{M}\mathcal{R}\hskip 1.00006pt\mathcal{C}^{i}\cap\mathcal{N}\mathcal{C}^{i+1}$ in order to finally settle the long-standing open question of how exactly the MapReduce classes correspond to the classical classes of parallel computation.