# Polar Codes with Memory

## TL;DR

This paper introduces polar codes with memory (PCM), which enhance error correction by sharing mutual information bits between consecutive blocks, significantly reducing packet error rate and latency across various decoding schemes.

## Contribution

The paper proposes PCM, a novel coding scheme that improves error correction and latency performance, compatible with multiple decoding algorithms, and demonstrates hardware implementations.

## Key findings

- PER decreases quadratically with PCM
- PCM achieves comparable PER to higher-list SCL decoding
- Hardware decoders significantly reduce latency and increase throughput

## Abstract

Polar codes with memory (PCM) are proposed in this paper: a pair of consecutive code blocks containing a controlled number of mutual information bits. The shared mutual information bits of the succeeded block can help the failed block to recover. The underlying polar codes can employ any decoding scheme such as the successive cancellation (SC) decoding (PCM-SC), the belief propagation (BP) decoding (PCM-BP), and the successive cancellation list (SCL) decoding (PCM-SCL). The analysis shows that the packet error rate (PER) of PCM decreases to the order of PER squared while maintaining the same complexity as the underlying polar codes. Simulation results indicate that for PCM-SC, the PER is comparable to (less than 0.3 dB) the stand-alone SCL decoding with two lists for the block length $N=256$. The PER of PCM-SCL with $L$ lists can match that of the stand-alone SCL decoding with $2L$ lists. Two hardware decoders for PCM are also implemented: the in-serial (IS) decoder and the low-latency interleaved (LLI) decoder. For $N=256$, synthesis results show that in the worst case, the latency of the PCM LLI decoder is only $16.1\%$ of the adaptive SCL decoder with $L=2$, while the throughput is improved by 13 times compared to it.