# Mixed-Signal Charge-Domain Acceleration of Deep Neural networks through Interleaved Bit-Partitioned Arithmetic

## TL;DR

This paper introduces a mixed-signal, charge-domain accelerator for deep neural networks that uses bit-partitioned arithmetic and switched-capacitor circuitry to improve power efficiency and reduce A/D conversion overhead.

## Contribution

It proposes a novel charge-domain architecture with bit-partitioned operations and switched-capacitor design, enabling low-power, high-parallelism DNN acceleration.

## Key findings

- Reduces A/D conversion overhead in DNN accelerators
- Improves noise mitigation through low-bitwidth operations
- Achieves efficient charge-domain computation with switched-capacitor circuits

## Abstract

Low-power potential of mixed-signal design makes it an alluring option to accelerate Deep Neural Networks (DNNs). However, mixed-signal circuitry suffers from limited range for information encoding, susceptibility to noise, and Analog to Digital (A/D) conversion overheads. This paper aims to address these challenges by offering and leveraging the insight that a vector dot-product (the basic operation in DNNs) can be bit-partitioned into groups of spatially parallel low-bitwidth operations, and interleaved across multiple elements of the vectors. As such, the building blocks of our accelerator become a group of wide, yet low-bitwidth multiply-accumulate units that operate in the analog domain and share a single A/D converter. The low-bitwidth operation tackles the encoding range limitation and facilitates noise mitigation. Moreover, we utilize the switched-capacitor design for our bit-level reformulation of DNN operations. The proposed switched-capacitor circuitry performs the group multiplications in the charge domain and accumulates the results of the group in its capacitors over multiple cycles. The capacitive accumulation combined with wide bit-partitioned operations alleviate the need for A/D conversion per operation. With such mathematical reformulation and its switched-capacitor implementation, we define a 3D-stacked microarchitecture, dubbed BIHIWE.