Increasing signal amplitude in electrical impedance tomography of neural activity using a parallel resistor inductor capacitor (RLC) circuit

TL;DR

This study introduces a parallel RLC circuit to enhance impedance signal amplitude in neural EIT, demonstrating significant increases in signal strength in vitro, which could improve spatial resolution and real-time imaging capabilities.

Contribution

The paper presents a novel application of a parallel RLC circuit in neural impedance tomography to significantly boost signal amplitude, aiding real-time imaging.

Findings

Impedance signal increased by up to 44% with RLC circuit.

Optimal frequency for RLC implementation was around 17 kHz.

Enhanced signal amplitude can improve spatial resolution in EIT.

Abstract

Objective: To increase the impedance signal amplitude produced during neural activity using a novel approach of implementing a parallel resistor inductor capacitor (RLC) circuit across the current source used in electrical impedance tomography (EIT) of peripheral nerve. Approach: Experiments were performed in vitro on sciatic nerve of Sprague-Dawley rats. Design of the RLC circuit was performed in electrical circuit modelling software, aided by in vitro impedance measurements on nerve and nerve cuff in the range 5 Hz to 50 kHz. Main results: The frequency range 17 +/- 1 kHz was selected for the RLC experiment. The RLC experiment was performed on four subjects using an RLC circuit designed to produce a resonant frequency of 17 kHz with a bandwidth of 3.6 kHz, and containing a 22 mH inductive element and a 3.45 nF capacitive element. With the RLC circuit connected, relative increases in the impedance signal (+/- 3sig noise) of 44 % (+/-15 %), 33 % (+/-30 %), 37 % (+/-8.6 %), and 16 % (+/-19 %) were produced. Significance: The increase in impedance signal amplitude at high frequencies, generated by the novel implementation of a parallel RLC circuit across the drive current, improves spatial resolution by increasing the number of parallel drive currents which can be implemented in a frequency division multiplexed (FDM) EIT system, and aids the long term goal of a real-time FDM EIT system by reducing the need for ensemble averaging.