Automatic Conversion from Flip-flop to 3-phase Latch-based Designs

TL;DR

This paper introduces an automated method to convert flip-flop based designs into 3-phase latch-based circuits, achieving similar performance with fewer latches, area, and power consumption.

Contribution

A novel automated flow for converting flip-flop designs to 3-phase latch-based designs, improving efficiency and reducing resource usage.

Findings

21.3% reduction in latches

5.8% area savings

16.3% power reduction

Abstract

Latch-based designs have many benefits over their flip-flop based counterparts but have limited use partially because most RTL specifications are flop-centric and automatic conversion of FF to latch-based designs is challenging. Conventional conversion algorithms target master-slave latch-based designs with two non-overlapping clocks. This paper presents a novel automated design flow that converts flip-flop to 3-phase latch-based designs. The resulting circuits have the same performance as the master-slave based designs but require significantly less latches. Our experimental results demonstrate the potential for savings in the number of latches (21.3%), area (5.8%), and power (16.3%) on a variety of ISCAS, CEP, and CPU benchmark circuits, compared to the master-slave conversions.