An Explicit Model for Ultra-thin Gate-All-Around Junctionless Nanowire FETs, Including 2D Quantum Confinement

TL;DR

This paper presents an explicit model for ultra-thin junctionless nanowire FETs that incorporates 2D quantum confinement effects, enabling accurate prediction of their DC electrical behavior across all operational regimes.

Contribution

The paper introduces a novel explicit modeling approach that accounts for 2D quantum confinement in ultra-thin junctionless nanowire FETs, validated against TCAD simulations.

Findings

Model accurately predicts device behavior in all operational regions.

Incorporates 2D quantum confinement effects into the DC model.

Validated with TCAD simulations across various device states.

Abstract

In this paper, we develop an explicit model to predict the DC electrical behavior in ultra-thin surrounding gate junctionless nanowire FET. The proposed model takes into account 2D electrical and geometrical confinements of carrier charge density within few discrete sub-bands. Combining a parabolic approximation of the Poisson equation, first order perturbation theory for the Schrodinger subband energy eigenvalues, and Fermi-Dirac statistics for the confined carrier density leads to an explicit solution of the DC characteristic in ultra-thin junctionless devices. Validity of the model has been verified with technology computer-aided design simulations. The results confirms its validity for all regions of operation, i.e., from deep depletion to accumulation and from linear to saturation. This represents an essential step toward analysis of circuits based on junctionless nanowire devices.

Tables

Table 1. Table 1: Physical Parameters of GAA JL Nanowire FET used in the TCAD simulations and Model derivations

Parameter	Symbol	Value
Channel Doping	$N_D$	${10}^{19}$ cm-3
Channel Thickness	$T_{sc}$	$3-5$ nm
Oxide Thickness	$t_{ox}$	$1$ nm
Channel Width	$L_G$	$1.2$ $\mu$m
Permittivity in Vacuum	${\epsilon }_o$	$8.85\times {10}^{-12}$ F/m
Silicon Permittivity	${\epsilon }_{si}$	$11.7{\epsilon }_o$
Silicon Oxide Permittivity	${\epsilon }_{ox}$	$3.9{\epsilon }_o$
longitudinal Effective mass	$m_l$	$0.916m_o$
Transverse Effective mass	$m_t$	$0.19m_o$
Silicon Band Gap	$E_g$	$1.12$ eV
Gate Work Function	$\Delta {\varphi }_m$	$4.8$ eV
Conduction Band effective DoS	$N_c$	$2.8\times {10}^{19}$ cm-3
Valence Band Effective DoS	$N_v$	$1.04\times {10}^{19}$ cm-3
Silicon Intrinsic Carrier Density	$n_i$	$1.45\times {10}^{10}$ cm-3
Temperature	$T$	${300}^{\circ }$ K
Mobility	${\mu }_n$	$90.5$ cm-3/V.S
Thermal Voltage	$v_t$	$0.025$ V

Equations

$$\psi (x,y)={\psi }_s-2({\psi }_s-{\psi }_c)\left[\frac{x}{T_{sc}}\left(1-\frac{x}{T_{sc}}\right)+\frac{y}{T_{sc}}\left(1-\frac{y}{T_{sc}}\right)\right]$$

$${Q}_{sc}=-4{{\varepsilon}_{si}}{T}_{sc}\frac{\partial\psi(x,y)}{\partial y}\bigg{|}_{int}=8{{\varepsilon}_{si}}\Delta V,$$

$$V_{ox}(y)+\psi (0,y)=V_{ox}(x)+\psi (x,0)=V_{GS}-{\Delta \varphi }_{ms}.$$

$$\begin{array}{r}{\bar{V}}_{ox}=V_{GS}-{\Delta \varphi }_{ms}-\frac{1}{T_{sc}}\left(\underset{0}{\overset{\frac{T_{sc}}{2}}{\int }}\psi (0,y)dy+\underset{0}{\overset{\frac{T_{sc}}{2}}{\int }}\psi (x,0)dx\right)\end{array}$$

$${\psi }_s=V_{GS}-{\Delta \varphi }_{ms}+\Delta V\left(\frac{1}{3}-2\frac{C_{si}}{C_{ox}}\right)$$

$$E_{k,n_x,n_y}=\frac{{\hslash }^2{\pi }^2{n}_x^2}{2m_{kx}^{\ast }{T}_{sc}^2}+\frac{{\hslash }^2{\pi }^2{n}_y^2}{2m_{ky}^{\ast }{T}_{sc}^2},$$

$$\Psi (x,y)=\sqrt{\frac{2}{T_{sc}}}\sin \left(\frac{\pi n_{x}x}{T_{sc}}\right)+\sqrt{\frac{2}{T_{sc}}}\sin \left(\frac{\pi n_{y}y}{T_{sc}}\right),$$

$$E_{n_x,n_y}^p=q\underset{0}{\overset{T_{sc}}{\int }}\underset{0}{\overset{T_{sc}}{\int }}\left\{{\left[\Psi (x,y)\right]}^{\ast }\psi (x,y)\left[\Psi (x,y)\right]\right\}dxdy.$$

$$E_{n_y,n_x}^p=q\Delta V\left(\frac{2}{3}+\frac{1}{n_x^2{\pi }^2}+\frac{1}{n_y^2{\pi }^2}\right).$$

$$E_{k,n_x,n_y}^T=E_{k,n_x,n_y}+E_{n_y,n_x}^p.$$

$$Q_{sc}=Q_m+Q_{fix},$$

$$Q_m=-\sum _{k=1}^{2}qDO{S}_k{F}_{-\frac{1}{2}}\left(-\frac{\eta }{K_{B}T}\right),$$

$$\eta =E_{k,n_x,n_y}^T-q{\psi }_s+q{V}_{ch},$$

$$I_{DS}=-\frac{\mu q}{L_G}\underset{{\eta }_S}{\overset{{\eta }_D}{\int }}{Q}_{m}d{V}_{ch}$$

$$I_{DS}=\frac{\mu }{L_G}\sum _{K=1}^{2}qDo{S}_K\underset{{\eta }_S}{\overset{{\eta }_D}{\int }}{F}_{-\frac{1}{2}}\left(-\frac{\eta }{K_{B}T}\right)\frac{d{V}_{ch}}{d\eta }d\eta .$$

$$\frac{d\eta }{d{V}_{ch}}=q\left[1+\frac{d{\psi }_s}{d{V}_{ch}}\left(\frac{d{E}_{k,n_x,n_y}^T}{d{\psi }_s}-1\right)\right].$$

$$\frac{d{\psi }_s}{d{V}_{ch}}=\frac{1}{\beta {\epsilon }_{ox}}\frac{d{Q}_m}{d{V}_{ch}}.$$

$$\frac{d{E}_{k,n_x,n_y}^T}{d{\psi }_s}=\frac{d{E}_{k,n_x,n_y}^T}{d\Delta V}\frac{d\Delta V}{d{\psi }_s}.$$

$$\frac{d{E}_{k,n_x,n_y}^T}{d{\psi }_s}=2\left(\frac{1}{3}+\frac{1}{n^2{\pi }^2}\right){\left(\frac{1}{3}-2\frac{C_{si}}{C_{ox}}\right)}^{-1}=a.$$

$$\frac{d\eta }{d{V}_{ch}}=q\left[1+\left(a-1\right)\left(\frac{1}{\beta {\epsilon }_{ox}}\frac{d{Q}_m}{d{V}_{ch}}\right)\right].$$

$$\frac{d\eta }{d{V}_{ch}}=q\left[1+\alpha \sum _{k=1}^{2}qDo{S}_k\frac{d{F}_{-\frac{1}{2}}(-\frac{\eta }{K_{B}T})}{d\eta }\frac{d\eta }{d{V}_{ch}}\right],$$

$$\frac{d{V}_{ch}}{d\eta }=\left[\frac{1}{q}-\alpha \sum _{k=1}^{2}qDo{S}_k\frac{d{F}_{-\frac{1}{2}}(-\frac{\eta }{K_{B}T})}{d\eta }\right].$$

$$\begin{split}&{{I}_{DS}}=\frac{\mu}{L_{G}}\sum\limits_{K=1}^{2}q{Do{{S}_{K}}}\int\limits_{{\eta}_{S}}^{{\eta}_{D}}{{{{F}_{-\frac{1}{2}}}}\left(-\frac{\eta}{{{K}_{B}T}}\right)}\\ &\times d\eta\Bigg{[}\frac{1}{q}-\alpha\sum\limits_{k=1}^{2}{qDo{{S}_{k}}\frac{d{{F}_{-\frac{1}{2}}}(-\frac{\eta}{{{K}_{B}}T})}{d\eta}}\Bigg{]}.\end{split}$$

$$\begin{split}&{{I}_{DS}}=\frac{\mu{{K}_{B}}T}{{{L}_{G}}}\sum\limits_{k=1}^{2}{Do{{S}_{k}}}\left[{{F}_{\frac{1}{2}}}(-\frac{\eta}{{{K}_{B}}T})\right]_{{{\eta}_{S}}}^{{{\eta}_{D}}}\\ &-\frac{\mu\alpha}{2{{L}_{G}}}\sum\limits_{k=1}^{2}{{{q}^{2}}DoS_{k}^{2}}\left[\Bigg{(}{{F}_{-\frac{1}{2}}}(-\frac{\eta}{{{K}_{B}}T})\Bigg{)}^{2}\right]_{{{\eta}_{S}}}^{{{\eta}_{D}}},\\ \end{split}$$

Full text

{IEEEkeywords}

Gate-All-Around FETs, Junctionless FETs, Nanowire FETs, Quantum Well, Ultra-thin Body Silicon on Insulator (UTBSOI).

1 Introduction

\IEEEPARstart

Junctionless (JL) Silicon Nanowire FETs used heavily doped channel to relax several critical fabrication steps and to obviate formation of source/channel and drain/channel junctions, which degrade the performance of short channel devices [1]. To deploy full advantages of Gate-All-Around (GAA) JL devices, several compact model have been proposed so far. Particularly in [2], [3], we developed a charge-based model, using Poisson-Boltzmann equations to model planar and cylindrical junctionless field effect transistors (JLFETs). This model, works for JLFETs with the channel thicknesses down to 10 nm and the device characteristics are well-captured by the proposed model. Nevertheles, this model neglects charge quantization into discrete subband, which is not a valid assumption as channel size decrease below 10 nm. As demonstrated in Fig. 1, the classic charge-based model in [3] fails to predict the charge density in the channel thickness of $T_{SC}=4$ nm.

To accurately capture the quantization effect, a coupled Poisson-Schrödinger equation (PS) needs to be solved self-consistently.This is a time-consuming calculation method and computationally not suitable for compact modeling purposes. Another work [4] proposed to incorporate the influence of charge quantization as a shift in the DC characteristics. However, due to the coupling between Poisson and Schrödinger equations, this shift varies with the gate to source voltage and therefore this method is not valid in all regions of operation. Lately, taking into account 1D quantum confinement, we developed an analytical approach for ultra-thin junctionless double-gate FETs, which introduces a zero order approximation in the wave-functions and a first order correction for the confined energies in all the regions of operation [5]. In this context, extending the proposed approach we derive an explicit model for junctionless GAA nanowire FET with ultra-thin rectangular cross section.

2 Device structure and Model Derivation

We assume an n-type junctionless nanowire GAA with a rectangular cross section perpendicular to $Z$ direction, shown in Fig. 2(a) where both the channel thickness (along vertical direction, i.e. $Y$) and the channel width (along lateral direction, i.e. $X$) are equal to ${T}_{sc}$ and the gate oxide thickness is ${t}_{ox}$ all around the silicon channel. The silicon channel is doped uniformly with a high level of donor concentration i.e. ${N}_{D}$ and other physical parameters are given in Table I, used in the model derivations and TCAD simulations. The principle of operation for junctionless devices is different from the regular junction-based double-gate device as the current flows through the volume instead of Si$-$SiO2 interfaces [6]. A junctionless nanowire FET transistor has three modes of operation [2]: While the gate to source potential, i.e. ${V}_{GS}$, is below the flat-band condition at the source terminal, i.e. ${V}_{FB,S}$ device operates in depletion mode. Whereas ${V}_{GS}$ is above the flat-band condition at the drain terminal, i.e. ${V}_{FB,D}$ device is in the accumulation region. A peculiar situation inherent to junctionless FETs is when depletion and accumulation coexist inside the channel, what is called hybrid channel state [2]. This happens when part of the channel near the source is in depletion whereas it turns into accumulation near the drain.

In the following section, applying the proposed treatment in [7] for 2D carrier confinement, the electrostatic potential profiles are accurately predicted in junctionless GAA nanowire FET for $3$ to $5$ nm silicon thicknesses.

3 Electrostatics in Ultrathin Junctionless GAA nanowire FETs

The 3D electrostatic potential distribution obtained from the TCAD simulation results is shown in Fig. 2(b) for $V_{GS}=0.3$ V and $4$ nm channel thickness doped at $10^{19}$cm*-3*. Here, we propose to follow the same approach in [8], and to assume a parabolic approximation for the 2D potential distribution $\psi(x,y)$ in lateral and vertical directions in an ultra-thin junctionless GAA (for both depletion and accumulation regions). Therefore, the parabolic approximation can be expressed as:

[TABLE]

as shown in Fig. 2(c) ${\psi}_{c}$ and ${\psi}_{s}$ are respectively the electrostatic potentials at the center and corners of the rectangular channel. In addition, the boundary conditions arising from the continuity of the displacement vectors at the four silicon-insulator interfaces of the square cross section give the total semiconductor charge per unit length: ${Q}_{sc}=4{{\varepsilon}_{si}}{{E}_{sc}}{{T}_{sc}}$, where ${E}_{sc}$ is the magnitude of the electric field, obtained from (1). Therefore,

[TABLE]

where $\Delta V={\psi}_{s}\!-\!{\psi}_{c}$ is directly proportional to ${Q}_{sc}$. The total charge density is shared among four silicon-insulator capacitors around the channel and an average voltage drop over the gate oxide barrier is defined by $\bar{V}_{ox}={Q}_{sc}/4{C}_{ox}{T}_{sc}$ where ${C}_{ox}\!=\!{{{\varepsilon}_{ox}}}/{{{t}_{ox}}}$ corresponds to the gate oxide capacitance per unit area. On the other hand, $V_{ox}$ varies along the channel interface, leading to

[TABLE]

To account for this and to obtain ${\psi}_{s}$, we integrate (3) around each corner of the rectangle. For instance, once integrating (3) at $x=0$ and $y=0$ from $y=0$ to $y={T}_{sc}/{2}$ over $y$-axis and from $x=0$ to $x={T}_{sc}/{2}$ over the $x$-axis leads to the following expression for $\bar{V}_{ox}$:

[TABLE]

By substituting the terms of ${\psi}(x,0)$ and ${\psi}(0,y)$ obtained from (1) into (4), we get $\bar{V}_{ox}$, leading to a key relation between ${\psi}_{s}$, ${V}_{GS}$ and $\Delta V$:

[TABLE]

where ${C}_{si}\!=\!{{{\varepsilon}_{si}}}/{{{T}_{sc}}}$ corresponds to semiconductor capacitance per unit area. Next, relying on the 1st order perturbation theory, we formulate the charge quantization in discrete sub-bands. Due to two-dimensional (2D) geometrical and electrical confinements in ultra-thin nanowire, mobile charges are confined in discrete sub-bands which are the solutions of the Schrödinger equation in the $x$, $y$ plane. An analytical solution can be obtained by assuming an ideal infinite potential well boundary condition at Si-SiO2 interface along with the 1st order perturbation potential inside the channel. For zero order solution, sub-bands energies and wave-functions are given by:

[TABLE]

[TABLE]

where $\Psi$ is the 2D wave function, and $\psi(x,y)$ is the 2D electrostatic potential in the channel and ${m}_{kx}^{*}$ and ${m}_{ky}^{*}$ are electron effective mass which depends on silicon orientation. In case of $<\!100\!>$ orientation, three different series must be considered to properly account for 6 valleys of the effective mass ellipsoid. $({m}_{kx}^{*},{m}_{ky}^{*})={(m_{l},m_{t}),(m_{t},m_{l}),(m_{t},m_{t})}$, $m_{l}=0.916m_{0}$ and $m_{t}=0.19m_{0}$ are the longitude and transversal effective mass of electron in silicon, respectively. ${n}_{x}$ and ${n}_{y}$ are the quantum numbers for $x$ and $y$ directions that starting from $({n}_{x},{n}_{y})=(1,1)$ which is the first sub-band. For the first sub-band, due to the degeneracy of 6 valleys in two groups, only two degenerate energy levels exist. The first order correction to the energy eigenvalues is computed using the time-independent perturbation theory:

[TABLE]

Replacing ${\psi}_{s}$ obtained from (5) into (1), and the resulting $\psi(x,y)$ in (8), the integral can be solve analytically and the first order correction of sub-band energies is obtained as a function of $\Delta V$, given by

[TABLE]

The total energy arising from geometrical and electrical confinements is the summation of (6) and (9), given by

[TABLE]

The term of $E_{k,{{n}_{x}},{{n}_{y}}}^{T}$ is measured from the reference of the surface electron energy $-q{\psi}_{s}$ as shown in Fig. 2(d). Total semiconductor charge density per unit length in the nanowire is the sum of fixed charges and mobile charges:

[TABLE]

where ${{Q}_{fix}}=q{{N}_{D}}T_{sc}^{2}$ represents the fix charge density per unit length and ${{Q}_{m}}$ is corresponding to the mobile charge density which can be written by using Fermi integral in order of $-\frac{1}{2}$ as function of $\Delta V$:

[TABLE]

where $\eta$ is the distance between the sub-band level and electron quasi-Fermi level in the channel, i.e $q{V}_{ch}$, the latter varies from [math] at source to $-q{V}_{DS}$ at the drain, therefore,

[TABLE]

and $Do{{S}_{k}}={g}_{k}\sqrt{\frac{2m_{k}^{*}{{K}_{B}}T}{{{\hbar}^{2}}{{\pi}^{2}}}}$ is one dimensional (1D) effective density of states in nanowire cross section and ${{g}_{k}}$ is the degeneracy factor, $(g_{1},g_{2})=(4,2)$ for the first sub-band. For a given bias point, (5) and (10) describe the surface potential ${\psi}_{s}$ and sub-band energy, $E_{k,{{n}_{x}},{{n}_{y}}}^{T}$, as a function of $\Delta V$. Replacing $Q_{sc}$ from (2) and $Q_{m}$ from (12) into (11), a single charge-based equation is solved semi-analytically to obtain the electron energy level, potential profile, and charge density. Fig. 3 shows the surface and center potentials and $\Delta V$ as a function of ${V}_{GS}$. In depletion mode (for small value of ${V}_{GS}-\Delta\phi_{ms}$), the mobile charge density is almost negligible, therefore $\Delta V$ is equal to $-qN_{D}T_{sc}^{2}/(8\varepsilon_{si})$, and the channel center potential becomes higher than the surface potential, causing an electrical confinement of the carriers wave-function into discrete 2D sub-bands, which enhances the geometrical 2D confinement in the channel. By increasing (${V}_{GS}$ toward the $V_{FB}$ this electrical confinement is relaxed. Fig. 4(a) and 4(b) shows degenerate energy levels for the first sub-band $({n}_{x},{n}_{y})=(1,1)$ versus ${V}_{GS}$ for various channel thickness ($T_{sc}=3,4,5$ nm). This figure clearly shows that the electrical confinement is relaxed by increasing the gate voltage up to the flat-band potential. Fig. 5 represents the mobile charge density versus the effective gate voltage for different channel thicknesses i.e. $T_{sc}=3-5$ nm calculated from the proposed model and verified by two-dimensional TCAD simulations results.

4 Derivation of the Drain Current

As in [9], relying on the drift-diffusion transportation model, we propose to calculate the drain current, given by:

[TABLE]

where $\mu$ is the free carrier mobility. We intentionally assume a constant mobility to focus on the essentials of electrostatics. Here, ${\eta}_{S}=E_{k,{{n}_{x}},{{n}_{y}}}^{T}-q{\psi}_{s}$ and ${\eta}_{D}=E_{k,{{n}_{x}},{{n}_{y}}}^{T}+q{V}_{DS}-q{\psi}_{s}$ represent the differences between the sub-band and quasi-Fermi levels at the source and drain sides. Replacing (12) into (14), and applying the chain rule for d${V}_{ch}$, we can write:

[TABLE]

The term of ${dV_{ch}}/{d\eta}$ is obtained from the definition of $\eta$ as:

[TABLE]

Replacing $\Delta V$ from (2) into (5), we can write: ${{V}_{GS}}-{\Delta{\phi}_{ms}}-{{\psi}_{s}}=-{{Q}_{sc}}/{{\beta\varepsilon}_{ox}}$, where $\beta={24\varepsilon_{si}}/({\varepsilon_{ox}-6\varepsilon_{si}})$. Differentiating both sides of this relationship with respect to the ${V}_{ch}$ we get:

[TABLE]

Next, applying the chain rule, ${d{E_{k,{{n}_{x}},{{n}_{y}}}^{T}}}/{d{{\psi}_{s}}}$ is obtained as follows

[TABLE]

Using (5) and (10) we can express (18) by

[TABLE]

Now we can rewrite (16) based on (17) and (19) as follows

[TABLE]

Replacing derivative of $Q_{m}$ with respect to ${V}_{ch}$ from (12) into (20) we have

[TABLE]

where $\alpha=(a-1)/\beta\varepsilon_{ox}$ taking into account (19) depends on channel and oxide thickness, therefore ${dV}_{ch}/{d\eta}$ is given by

[TABLE]

Applying (22) into (15) we can obtain the drain current

[TABLE]

Integrating (23) from source to drain we get

[TABLE]

Fig. 6 and Fig. 7 show the drain current versus the effective gate voltage for low ${V}_{DS}$ ($=0.1$ V) and high ${V}_{DS}$ ( $=0.7$ V) respectively, the length of the channel is ${L}_{G}=1.2$ $\mu$m to avoid any short and narrow channel effects. The result predicted by the model shows excellent agreement with TCAD simulations, in both linear and saturation conditions for both charge depletion and accumulation modes. This confirms validation of the model under every operation regions.

Finally, it is worth mentioning that to derive the proposed analytical model, few approximations have been made. First, we assumed infinite quantum well with the first order perturbation theory for sub-band energy estimation and we estimated the potential distribution in channel cross-section by using the parabolic approximation, besides, only the contribution of the first sub-band has been considered in the drain current derivation. These approximations are valid for ultra-thin silicon channel. Nevertheless, as $T_{sc}$ increases above $6$ nm, the mobile charge density is distributed non-uniformly near the boundaries of the silicon channel and forms a triangular quantum well, which causes a deviation from the pre-assumed parabolic potential approximation and also affects sub-band energies. Moreover, the contribution of higher sub-bands should not be neglected due to the relaxation of geometrical confinement.

5 Conclusion

In this paper, we derived an analytical model to calculate the two dimensional electrostatic potential distribution in ultra-thin junctionless GAA nanowire FET with channel thickness in the range of $3$ to $6$ nm. Relying on the drift-diffusion transportation model, we have proposed an analytical model to calculate the drain current in ultra-thin junctionless GAA nanowire FET. The model is valid in all regions of operation, from deep depletion to accumulation and from linear to saturated regimes, as confirmed from a detailed comparison with the TCAD numerical simulations. The proposed model represents an essential step toward dc analysis of circuits/sensors-based on ultra-thin junctionless GAA nanowire FETs. This approach can be further used to derive a full transcapacitances [10, 11] equivalent circuit and short channel effects in ultra-thin junctionless GAA nanowire FETs [12].