Collecting and Presenting Reproducible Intranode Stencil Performance: INSPECT

TL;DR

This paper introduces INSPECT, an open-source framework for reproducible performance measurement and modeling of stencil algorithms across various hardware architectures, aiding developers in performance assessment and optimization.

Contribution

It presents a generalizable methodology, tools, and a collection of results for reproducible intranode stencil performance evaluation across multiple architectures.

Findings

Reproducible performance data for multiple stencil patterns

Validated performance models across different hardware

Open-source toolchain for performance analysis

Abstract

Stencil algorithms have been receiving considerable interest in HPC research for decades. The techniques used to approach multi-core stencil performance modeling and engineering span basic runtime measurements, elaborate performance models, detailed hardware counter analysis, and thorough scaling behavior evaluation. Due to the plurality of approaches and stencil patterns, we set out to develop a generalizable methodology for reproducible measurements accompanied by state-of-the-art performance models. Our open-source toolchain, and collected results are publicly available in the "Intranode Stencil Performance Evaluation Collection" (INSPECT). We present the underlying methodologies, models and tools involved in gathering and documenting the performance behavior of a collection of typical stencil patterns across multiple architectures and hardware configuration options. Our aim is to endow performance-aware application developers with reproducible baseline performance data and validated models to initiate a well-defined process of performance assessment and optimization.