# Clifford Gate Optimisation and T Gate Scheduling: Using Queueing Models for Topological Assemblies

## TL;DR

This paper uses queueing models to analyze Clifford gate optimization and T gate scheduling in topological quantum circuit assemblies, revealing potential hardware and time savings for certain circuits.

## Contribution

It introduces a queueing theory approach to model and evaluate topological assemblies, highlighting the impact of gate scheduling on resource efficiency.

## Key findings

- Assembly execution time remains constant under hardware restrictions for certain circuits.
- Queueing models effectively evaluate topological assembly performance.
- Optimizing Clifford and T gates can reduce hardware and execution costs.

## Abstract

Clifford gates play a role in the optimisation of Clifford+T circuits. Reducing the count and the depth of Clifford gates, as well as the optimal scheduling of T gates, influence the hardware and the time costs of executing quantum circuits. This work focuses on circuits protected by the surface quantum error-correcting code. The result of compiling a quantum circuit for the surface code is called a topological assembly. We use queuing theory to model a part of the compiled assemblies, evaluate the models, and make the empiric observation that at least for certain Clifford+T circuits (e.g. adders), the assembly's execution time does not increase when the available hardware is restricted. This is an interesting property, because it shows that T gate scheduling and Clifford gate optimisation have the potential to save both hardware and execution time.