# A Low-Power Domino Logic Architecture for Memristor-Based Neuromorphic Computing

## TL;DR

This paper introduces a low-power domino logic architecture tailored for memristor-based neuromorphic computing, leveraging memristor RC circuit delays for synaptic operations and synchronization schemes for efficient inter-layer communication.

## Contribution

The work presents a novel domino logic design that enhances energy efficiency in memristor-based neuromorphic systems, with a simple power model and synchronization methods for improved performance.

## Key findings

- Achieves 0.61 fJ per classification component energy efficiency.
- Outperforms existing designs in energy per accuracy metrics.
- Demonstrates effective synchronization for neural network layer communication.

## Abstract

We propose a domino logic architecture for memristor-based neuromorphic computing. The design uses the delay of memristor RC circuits to represent synaptic computations and a simple binary neuron activation function. Synchronization schemes are proposed for communicating information between neural network layers, and a simple linear power model is developed to estimate the design's energy efficiency for a particular network size. Results indicate that the proposed architecture can achieve 0.61 fJ per classification per component (neurons and synapses) and outperforms other designs in terms of energy per % accuracy.