Transport Triggered Array Processor for Vision Applications

TL;DR

This paper presents a transport triggered array processor optimized for vision applications, leveraging near-threshold operation and massive parallelism to enhance energy efficiency in low-power IoT devices.

Contribution

It introduces a programmable array processor based on Transport Triggered Architecture that compensates for low-speed near-threshold operation with massive parallelism for vision tasks.

Findings

Achieves high energy efficiency for local binary pattern computations.

Utilizes near-threshold voltage operation (Vdd=0.6V) to reduce power consumption.

Demonstrates effective parallelization to mitigate performance loss.

Abstract

Low-level sensory data processing in many Internet-of-Things (IoT) devices pursue energy efficiency by utilizing sleep modes or slowing the clocking to the minimum. To curb the share of stand-by power dissipation in those designs, near-threshold/sub-threshold operational points or ultra-low-leakage processes in fabrication are employed. Those limit the clocking rates significantly, reducing the computing throughputs of individual processing cores. In this contribution we explore compensating for the performance loss of operating in near-threshold region (Vdd =0.6V) through massive parallelization. Benefits of near-threshold operation and massive parallelism are optimum energy consumption per instruction operation and minimized memory roundtrips, respectively. The Processing Elements (PE) of the design are based on Transport Triggered Architecture. The fine grained programmable parallel solution allows for fast and efficient computation of learnable low-level features (e.g. local binary descriptors and convolutions). Other operations, including Max-pooling have also been implemented. The programmable design achieves excellent energy efficiency for Local Binary Patterns computations.