Using your ADC and Backend Capacitors to Authenticate for Free: (Virtually) Free from Database, Enrollment, and Excessive Area/Power Overhead

TL;DR

This paper introduces a novel, intrinsic, database-free chip authentication method using back-end capacitors integrated with ADCs, offering a more reliable and cost-effective alternative to traditional PUF-based techniques.

Contribution

It demonstrates how ADCs can be modified for capacitor-based authentication, eliminating the need for dedicated hardware and large signature databases.

Findings

Achieves intrinsic, database-free authentication using back-end capacitors.

Offers improved reliability over transistor PUFs due to insensitivity to temperature and aging.

Incurred 3.2% power and 75% active-area overhead, deemed acceptable given the benefits.

Abstract

Detection of counterfeit chips has emerged as a crucial concern. Physically-unclonable-function (PUF)-based techniques are widely used for authentication, however, require dedicated hardware and large signature database. In this work, we show intrinsic & database-free authentication using back-end capacitors. The discussed technique simplifies authentication setup and reduces the test cost. We show that an analog-to-digital converter (ADC) can be modified for back-end capacitor-based authentication in addition to its regular functionality; hence, a dedicated authentication module is not necessary. Moreover, since back-end capacitors are quite insensitive to temperature and aging-induced variations than transistors, the discussed technique result in a more reliable authentication than transistor PUF-based authentication. The modifications to conventional ADC incur 3.2% power overhead and 75% active-area overhead; however, arguably, the advantages of the discussed intrinsic & database-free authentication outweigh the overheads. Full version of this article is published at IEEE TVLSI.

Tables

Table 1. TABLE I: Comparison between PUF based authentication and our scheme.

Particulars	RO-PUF	Arbiter-PUF	This work
Temperature Sensitivity	42.25%	68.83%	5.11%
Aging induced Variations	87.97%	66.34%	3%
Average Power (W)	3.83$\times {10}^{-6}\times N_{INVs}$ per response bit	3.347$\times {10}^{-6}\times N_{Ds}$ per response bit	696.13$\mu$
Database-free	$X$	$X$	$✓$
Dedicated Hardware	$✓$	$✓$	$X$

Equations

$$A_F=P(C)\times P(\frac{Pass}{C})+P(A)\times (1-P(\frac{Pass}{A})),$$

$$P(\tfrac{Pass}{C})=\tfrac{1}{P(C)}\times\big{(}P(Pass)-P(A)\times P(\tfrac{Pass}{A})\big{)},$$

$$P(Pass)={\int }_{T_L}^{T_U}{f}_{AC}dx,P(\frac{Pass}{A})={\int }_{T_L}^{T_U}{f}_{AC|A}dx.$$

$$\begin{multlined}\textstyle A_{F|mult}=P(C)\times\sum_{S}P\Big{(}\tfrac{Pass}{C,AC_{1},AC_{2},...AC_{n}}\Big{)}+\\ \textstyle P(A)\times\sum_{S}P\Big{(}\tfrac{Fail}{A,AC_{1},AC_{2},...AC_{n}}\Big{)}.\end{multlined}\textstyle A_{F|mult}=P(C)\times\sum_{S}P\Big{(}\tfrac{Pass}{C,AC_{1},AC_{2},...AC_{n}}\Big{)}+\\ \textstyle P(A)\times\sum_{S}P\Big{(}\tfrac{Fail}{A,AC_{1},AC_{2},...AC_{n}}\Big{)}.$$

$$\frac{(C_{u,P,i}+C_{OF})\times V_{REF}}{{\sum }_{j=1}^N{C}_{u,P,i}+C_{OF}}+V_n(t)<\frac{C_{u,N,i}\times V_{REF}}{{\sum }_{j=1}^N{C}_{u,N,i}},$$

$$\frac{(C_{u,N,i}+C_{OF})\times V_{REF}}{{\sum }_{j=1}^N{C}_{u,N,i}+C_{OF}}+V_n(t)<\frac{C_{u,P,i}\times V_{REF}}{{\sum }_{j=1}^N{C}_{u,P,i}}.$$

$$C_{u,P,i}\sim C_{u,N,i}\sim \mathcal{N}(C_u,{\sigma }_{cu}^2),$$

$$V_n\sim \mathcal{N}(0,{\sigma }_n^2),$$

$${\sum }_{j=1}^N{C}_{u,P,i}\sim {\sum }_{j=1}^N{C}_{u,N,i}\sim \mathcal{N}(N\times C_u,{\sigma }_{cu}^2/N).$$

$$D_{Auth,W}=\sqrt{\sum _i{\eta }_i\times (N_{AC}(C_{OF,i})-N_{AC,AVG}(C_{OF,i}){)}^2}$$

$$C(T)=C(T_0)\times (1+TC\times (T-T_0)),$$

Full text

I Introduction

Counterfeit chips are becoming increasingly common and have emerged as a critical challenge for IC design and fabrication industry [1], [2]. The current mainstream approach to detect counterfeit chips is to embed a physically-unclonable-function (PUF) in the chips. A PUF exploits process variability in design process and produces an uncontrolled and unclonable signature. The output of a PUF in each authentic design is stored in a database. Counterfeit chips are detected by tallying their PUF signature against the database [Fig. 1 (a)]. However, PUF-based authentication has presented two critical challenges: (1) A PUF with adequately large signature size requires considerable area, power, and test overhead, presenting challenges for resource-limited platforms and time to market. (2) With exponential growth of electronic devices, maintaining and tallying against a database of PUF signatures is unwieldy and even impractical for certain applications [3].

Countering the above limitations of a PUF, an intrinsic and database-free authentication was presented in [4]. Intrinsic authentication discriminates authentic and counterfeit chips by exploiting their design and fabrication discrepancies. In Fig. 1 (b), for intrinsic authentication, a vendor not only ships an IC to a client but also authentication characteristics ($AC$s) and their expected range of output. $AC$s are designed such that there is a clear distinction between authentic and counterfeit chips. For instance, if a counterfeit chip uses an inferior foundry process or package to save cost (maximize profit) then there will be discrepancies in path delays. Likewise, an adversary pirating an IP may not be aware of the exact layout or routing/placement algorithms/parameters of various design components resulting in path delay discrepancies. Hence, path delays can be used as an $AC$ for authentication. In [4], an intrinsic authentication based on the delay of non-critical paths in scan-chains was presented.

However, $ACs$ in intrinsic authentication should be carefully chosen to minimize false positives and false negatives considering process, temperature, and aging-induced variations. Fig. 2 examines this using probability density function (PDF) for an $AC$ in all (authentic and counterfeit) designs, $f_{AC}$, and in authentic designs, $f_{AC|A}$. For authenticating thresholds $T_{L}$ $\&$ $T_{U}$ in Fig. 2, the authentication failure $A_{F}$ is expressed for counterfeit (C) and authentic (A) chips as

[TABLE]

Considering a testcase of $f_{AC}=\mathcal{N}(0.5,0.1)$ and $f_{AC|A}=\mathcal{N}(0.9,0.05)$ in Fig. 2(b), the variance in $f_{AC|A}$ limits the minimum $A_{F}$ under the optimal threshold bound. The observation extends to any $f_{AC}$ & $f_{AC|A}$. Therefore, $ACs$ showing a small variance from chip-to-chip is necessary for reliable intrinsic authentication. Additionally, multiple $ACs$ can be combined to improve accuracy. For example, an authentication test passes if at least $m$ out of total $n$ $ACs$ pass the test. In this case, authentication failure $A_{F|mult}$ is

[TABLE]

Here, $S$ spans over all possible outcomes of $AC_{1}...AC_{n}$. However, $ACs$ must be uncorrelated to minimize $A_{F|mult}$. For example, Fig. 2 (c) considers a test-case with two $ACs$ and accepting a chip if at least one of the two $ACs$ pass the test with $f_{AC}=\mathcal{N}(0.5,0.25)$, $f_{AC|A}=\mathcal{N}(0.9,0.1)$ and co-variance $\rho$=0.5. However, in Fig. 2 (c), if $ACs$ are correlated, minimum $A_{F|mult}$ is limited. Considering the above requirements on $ACs$ in intrinsic authentication, this work aims the following contributions:

• •

$ACs$* with small variance:* We discuss intrinsic $AC$ based on the standard deviation ($\sigma$) of unit back-end capacitances ($C_{u}$). Since the back-end capacitances are insensitive to temperature and aging-induced variations, and many unit-sized capacitances are typically used (e.g., in a 10-bit capacitive DAC, 256 $C_{u}$ are used), $\sigma$ of the unit capacitances can be reliably read for a low variance of $AC$.

• •

Low correlation to transistor-based $ACs$: Since the back-end process steps are typically uncorrelated to the front-end steps, the back-end capacitance-based $ACs$ discussed here have low correlation to transistor-based $AC$ in [4]. Therefore, a combination of $ACs$ presented here with transistor-based $ACs$ can enhance the robustness of authentication.

• •

Low overhead $AC$ extraction: SAR ADC architecture is modified to allow signature extraction using back-end capacitors. Compared to the conventional ADC, modified ADC requires 3.2% higher power at the same frequency and 75% higher active-area.

The present work also extends our prior work [5] where we first discussed the feasibility of intrinsic authentication using back-end capacitors. In this work, we advance the design by considering energy efficient monotonic switching SAR ADC architecture and by avoiding additional parasitics in the signal path to minimize overheads. We also discuss repeated sampling based signature extraction and optimization of ACs for enhanced reliability.

II Process-induced Variability in Metal-Oxide

-Metal (MOM) Capacitors

Poly-insulator-poly (PIP), metal-oxide-metal (MOM) and metal-insulator-metal (MIM) are the most widely used back-end capacitors. Currently, MOM capacitors are preferred over the others due to its reduced cost [6] and easy customization for very small capacitances for area/power-constrained designs. Therefore, we focus on MOM capacitor-based $ACs$. Line edge roughness (LER) is the primary source of variability in MOM capacitors [Fig. 3] and originates due to inaccuracies in lithography process such as metal edge roughness, limited resolution, random diffusion of acids, and intrinsic roughness of the resist used. Therefore, LER can be quite foundry-specific depending on the process steps, equipment, and composition of the process materials used in a facility. LER can be characterized by standard deviation ($\sigma_{LER}$) conveying absolute roughness amplitude information and correlation length ($\eta_{LER}$) conveying proximity of the adjacent edges. We consider LER-induced variability in MOM capacitance using Synopsys Sentaurus [7] based TCAD simulations on a hundred capacitor structures. Fig. 4 illustrates the impact of $\eta_{LER}$, $\sigma_{LER}$, and sizing on the variance characteristics of MOM capacitors. From Fig. 4 (a), it can be observed that decreasing the proximity of adjacent edges results in increased variance. In Fig. 4 (b), increasing $\sigma_{LER}$ results in increased variance. Fig. 4 (c) shows MOM capacitor variance at varying capacitor dimensions. Larger area capacitors have smaller variance, in agreement with the Pelgrom’s law [6]. In Fig. 4, if a cloned design (Fab 2) is fabricated using different $\eta_{LER}$ and/or $\sigma_{LER}$ or is unaware of the exact capacitor dimensions in the original (Fab 1), discrepancies arise in the capacitance variance.

III ADC-based Intrinsic Authentication exploiting MOM Capacitor Variability

III-A Brief Overview of SAR ADC Architecture and Operation

Conventional SAR ADC includes charge-redistribution capacitive digital-to-analog converter (CDAC), comparator, and successive approximation logic. SAR ADC with monotonic switching to achieve reduced switching energy has been proposed in [8], [9]. Fig. 5 (a) shows the diagram of 10-bit SAR ADC architecture, where faster reference settling is achieved by using downward switching. Fig. 5 (b) depicts the switching procedure. The input signal is sampled onto the top plates of the capacitors while the bottom plates are connected to Vref. Comparator performs the first comparison after the sampling phase. Depending on the comparator output, the bottom plate of the largest capacitor i.e, 256$\times$Cu on VIP terminal is connected to the ground if VIP$>$VIN, while the bottom plate of the largest capacitor on VIN side is connected to Vref. The connections are reversed on the two sides if VIN$>$VIP. Above procedure is continued till the decision for the lowest significant bit (LSB) is obtained.

III-B Authentication Scheme

III-B1 Modified ADC architecture

Fig. 6 shows the modified ADC architecture for intrinsic authentication using the back-end capacitors. Our technique uses the fact that larger capacitances in a CDAC are implemented using parallel combination of unit capacitances (Cu). Such implementation reduces the overall mismatch of the larger capacitances, but the mismatch in the unit elements cannot be decreased or eliminated. The circuit modifications provide access to each unit element forming a larger capacitor. Additionally, a programmable offset capacitance (COF) with COF $\sim$ $\sigma_{Cu}$ ($\sigma_{Cu}$ is the standard deviation of Cu) is implemented at both ends of comparator. COF is realized by connecting a programmable number of capacitances in series in Fig. 6 where each small capacitance is formed using lower overlap length.

III-B2 Authentication characteristic extraction

$AC$ in our scheme is defined by the number $N_{AC}$ of unit capacitance pairs at the positive and negative terminals of the comparator (i.e., $C_{u,P,i}$ & $C_{u,N,i}$) where $C_{u,P,i}>C_{u,N,i}+C_{OF}$ or $C_{u,N,i}>C_{u,P,i}+C_{OF}$. $N_{AC}$ characterizes the variance of Cu. Presently, only the unit capacitors for the maximum significant bit (MSB) in CDAC are utilized for $AC$. Signature extraction involves three steps: In Step 1, offset capacitance COF is connected to the negative input of the comparator in Fig. 7 (i). In Step 2, the top and bottom plates of all Cu in both MSB arrays and COF are discharged to the ground [Fig. 7 (ii)]. In Step 3, one capacitor from each MSB array and COF are activated by connecting their bottom plates to ‘1’ [Fig. 7 (iii)]. The above procedure is repeated for all Cu and the counter’s count is incremented if the comparator’s output is one. After this, COF is activated at the positive input of the comparator. The above steps are repeated and counter’s count is incremented when comparator’s output is zero. The entire procedure is repeated at varying COF to obtain the entire $AC$, i.e., $N_{AC}(C_{OF})$. At the foundry, the above experiment is repeated with a significant number of ICs to obtain multiple traces of $N_{AC}(C_{OF})$. From the obtained traces, average trace $N_{AC,AVG}(C_{OF})$ and expected bounds are determined and shipped to a client for intrinsic authentication.

III-C Simulation Results

Circuits utilized to perform the simulation study are implemented using 45nm technology [10]. MOM capacitor model based on [11] is considered. Fig. 8 shows the circuit diagram of dynamic comparator with PMOS input transistors. Outputs Outn and Outp are reset to VDD when clk=0. Differential input pair compares the voltages at the two input terminals when clk=1 and positive feedback action causes the drain potential at either M1 or M2 to become high. Inverters are used at the output stage for rail-to-rail output swing. Offset voltage in a comparator arises due to process variations and is deterministic in nature. Offset voltage can be reduced by using dynamic offset cancellation techniques such as chopping and auto-zeroing [12]. On the contrary, comparator input referred noise is indeterministic in nature and is considered to have a Gaussian distribution profile with zero mean and a variance of 250 nV2 in our simulations [13].

Fig. 9 shows the simulation results for $N_{AC}(C_{OF})$ normalized against the total Cu pairs. Monte-Carlo simulations are performed on a hundred designs. The impact of input referred noise is suppressed by repeated comparisons for the considered capacitor pair and taking the dominant comparator output as the final output. Fig. 9 (a) shows the extracted distribution when repeated sampling is not used. In Fig. 9 (a), $AC$ bounds are wider since the input referred noise dominates. Tighter bounds are achieved in Fig. 9 (b) by repeated sampling. Fig. 9 (c) explains the shift in the average trace of $N_{AC}(C_{OF})$ ($N_{AC,AVG}(C_{OF})$) under repeated sampling in Fig. 9(b). In a Cu pair ($C_{u,P,i}$, $C_{u,N,i}$), the distribution of $C_{u,P,i}-C_{u,N,i}$ follows a Gaussian distribution. The comparator identifies when |$$C_{u,P,i}-C_{u,N,i}$$| is more than COF. Since the density of $C_{u,P,i}-C_{u,N,i}$ decreases away from zero, a higher fraction of capacitor pairs is falsely characterized to have a higher mismatch than COF than the fraction falsely characterized to have a lower mismatch due to comparator noise. Repeated measuring corrects this inaccuracy which also results in $N_{AC,AVG}(C_{OF})$ moving to a lower value. To perform authentication, $N_{AC,AVG}(C_{OF})$ and the expected output bounds are stored. Authenticity of an IC is determined by considering the Euclidean distance ($D_{Auth}$) between its $N_{AC}(C_{OF})$ and $N_{AC,AVG}(C_{OF})$ and by comparing against the bounds. Notably, unlike PUF, where the authenticating database grows with the number of devices, the discussed scheme is database-free where $AC$ test is the same for all devices.

IV Discussion

In this section, we discuss the optimization considerations to $AC$ for the optimal number of capacitors to be utilized. Impact of temperature and aging-induced variations on proposed technique is investigated. Subsequently, resource overhead incurred due to modifying conventional SAR ADC architecture has been discussed.

IV-A Optimizing Authenticating Characteristics

We optimize the discussed $AC$ for the following objectives. $\mathcal{O}_{1}$: Maximize the sensitivity of the authentication metric $D_{Auth}$ to the variance of $C_{u}$. $\mathcal{O}_{2}$: Minimize the variance of $D_{Auth}$ (note that $D_{Auth}=||N_{AC}(C_{OF})-N_{AC,AVG}(C_{OF})||$). At a COF, $N_{AC}$ in Fig. 9 is incremented if the following inequalities hold

[TABLE]

[TABLE]

Here, $C_{u,P,i}$ & $C_{u,N,i}$ is the $i^{th}$ capacitance pair at the positive and negative terminals of the comparator, respectively. $V_{REF}$ is the reference potential to charge the capacitance at the state ‘1’. $V_{n}$ is time dependent input referred noise to the comparator. $N$ is the number of capacitors used for $AC$. Various quantities in (3) & (4) follow the distributions below

[TABLE]

[TABLE]

[TABLE]

Here, $\sigma_{Cu}$ is the standard deviation of $C_{u}$ mismatch and $\sigma_{n}$ is the standard deviation of input referred noise. From (3-4), although using a fewer number of capacitors (small $N$) is statistically unreasonable, using a very large number of capacitors also reduces the sensitivity of the comparator’s output to the mismatch in $C_{u,P,i}$ & $C_{u,N,i}$ and the output is dominated by $V_{n}(t)$. Considering the probability distributions in (5-7), Fig. 10 shows variance and mean of $D_{Auth}$ as a function of $N$. In Fig. 10 (a), variance of $D_{Auth}$ reduces at higher $N$ and tighter bounds can be implemented for authentication. However, in Fig. 10(b), sensitivity of $N_{AC,AVG}$ to $\Delta C_{OF}$ also decreases as we increase $N$ (shown mean($D_{Auth}$) traces at $C_{OF}$ = $C_{u}$/50 $\&$ $C_{u}$/100), imposing an upper limit on $N$. Trade-offs between Fig. 10 (a) and (b) determine the optimal value of capacitors ($N_{OPT}$) used for authentication.

The optimization for $\mathcal{O}_{1}$ can be further enhanced by using a weighted distance of $N_{AC}$ against $N_{AC,AVG}$ at varying COF,

[TABLE]

where $D_{Auth,W}$ denotes the weighted distance between $N_{AC}$ and $N_{AC,AVG}$, and $\eta_{i}$ denotes the weight at $C_{OF,i}$. We assign $\eta_{i}$ proportional to the sensitivity of $D_{Auth}$ to $C_{OF}$ (sensitivity = $\Delta D_{Auth}/\Delta C_{OF}$). In Fig. 11 (a), $D_{Auth}$ is more sensitive to $\sigma_{C_{u}}$ at higher $C_{OF}$. In Fig. 11(b), the reliability of the authentication scheme is enhanced by performing such weighted analysis, where $D_{Auth,W}$ exhibits higher sensitivity to $\sigma_{C_{u}}$ variations than $D_{Auth}$ and improves the discernibility even at lower $\sigma_{C_{u}}$.

IV-B Impact of Temperature and Process Variation

Discussed authentication scheme exploits process variations in capacitors. However, variation of capacitance as a function of temperature is undesired. The expression for capacitance as a function of temperature is given below

[TABLE]

where $TC$ denotes the temperature co-efficient for capacitance variation. Note that the temperature sensitivity of the back-end capacitors is much less than in transistors. Additionally from (3-4), the temperature dependence in our scheme is suppressed since the signature extraction depends on the capacitance ratio which is even less sensitive to temperature. In this context, we have studied the impact of temperature variations on $N_{AC,AVG}$ ($C_{OF}$). In Fig. 12 (a), $N_{AC,AVG}$ ($C_{OF}$) is fairly insensitive to temperature variations. Also, sensitivity analysis in Fig. 12 (b) (Temperature Sensitivity = $\Delta N_{AC,AVG}(C_{OF})/\Delta T$) shows that capacitance ratio based signature extraction is highly resilient to temperature variations, providing reliable estimate of $N_{AC,AVG}(C_{OF})$.

Moreover, process variability in CMOS circuitry only has a second order effect to the robustness of discussed authentication since the authentication primarily depends on capacitors. We earlier discussed comparator offset reduction using [12]. In Fig. 12 (c), we have studied the impact of process corner variation in transistors of peripheral circuitry on $N_{AC,AVG}$ ($C_{OF}$). Additionally, sensitivity analysis of the discussed scheme for different process corners computed as $\Delta N_{AC,AVG}(C_{OF})/\Delta V_{th}$ is shown in Fig. 12 (d). Global $V_{th}$ variations in transistors (especially in those used in comparator) does not affect extracted signature $N_{AC,AVG}$ ($C_{OF}$) significantly and efficiently captures mismatch information from capacitors.

IV-C Overheads to the Regular Operation of ADC

Resource overhead in the modified SAR ADC arises as a result of using additional inverters to access unit elements of MSB capacitor. Further, control logic used for controlling signature extraction and ADC operation leads to additional overhead. Fig. 12 (e) depicts the HSPICE simulated switching sequence of conventional & modified ADCs. Incorporated modifications preserve the switching sequence. The conventional and modified ADC architectures can be reliably operated at a maximum frequency of 205.2 MHz, thus, modifications incorporated does not affect the maximum operating frequency. Fig. 12 (f) shows the plot for power $vs$ performance analysis where modified ADC consumes $\sim$ 3.2% higher power than the conventional design while operating at 205.2 MHz. Further, modified ADC has an active area overhead of 75% when compared to conventional ADC. Active area is computed by adding up $L\times W$ of all the transistors. It should be noted that overhead can be further reduced by decreasing $N$; leading to simplified control logic design as well as reducing number of additional inverters. However, this can critically degrade authentication reliability.

IV-D Comparison between PUF and Intrinsic Authentication

Table I summarizes the comparison between PUF based authentication [14, 15] and our scheme. PUF-based authentication requires dedicated hardware and database of challenge-response pairs (CRPs). Whereas our scheme is intrinsic and can utilize the existing components (in this paper, an ADC) for authentication. In Table I, the sensitivity for temperature and aging-induced variations in PUF designs has been computed as percentage change in average frequency difference (RO PUF) and average delay difference (arbiter PUF) for 30oC change in temperature and 10% change in Vth of transistors, respectively. Proposed scheme manifests better resilience to temperature and aging induced variations compared to RO & arbiter PUFs by relying on the back-end capacitors which are more temperature/aging-insensitive than front-end components. Further, power consumption in PUF scales with CRPs where the number of CRPs depends on the number of on-field devices. Power consumption of PUF in Table I is shown as a function of the number of inverters (NINVs) in RO PUF & number of delay elements (NDs) in Arbiter PUF decided by NCRPs [14], [15]. Meanwhile, the proposed solution is database-free; hence, the power dissipation of the scheme is not determined by the number of on-field devices. Thus, the proposed scheme can better suit applications with a very large number of on-field devices.

V Conclusion

Mismatch in back-end capacitors is efficient source for authentication. In this work, MOM capacitor based authentication technique has been proposed using SAR ADC to extract the signature. Proposed authentication scheme does not require dedicated hardware as it utilizes invariably present ADC block. Moreover, our scheme is database-free unlike PUF based authentication. Discussed authentication scheme achieves better reliability than transistor based techniques as back-end capacitors are fairly insensitive to temperature and aging induced variations. Additionally, power consumption in our scheme does not depend on number of on-field devices, which is not the case with PUFs. Although, incorporated modifications to the conventional SAR ADC architecture incur 3.2% power overhead and 75% active area overhead, advantages of our intrinsic and database-free authentication can supersede overhead in many applications.

VI Acknowledgment

This work is an outcome of research undertaken in the project supported by Semiconductor Research Corporation (SRC) under grant 2712.022.