Josephson Junction Field-effect Transistors for Boolean Logic Cryogenic Applications

TL;DR

This paper explores Josephson junction FETs as potential low-power, cryogenic Boolean logic and memory elements, demonstrating their feasibility through modeling and circuit simulations, highlighting their advantages for cryogenic computing.

Contribution

It introduces a model and simulation framework for JJ-FET-based logic gates, showing their potential for cryogenic low-power digital applications.

Findings

JJ-FETs can be used for cryogenic Boolean logic and memory.

Circuit simulations indicate feasibility of signal restoration and fanout.

JJ-FETs are promising for low-power, clocked cryogenic logic.

Abstract

Josephson junction field effect transistors (JJ-FET) share design similarities with metal-oxide-semiconductor field effect transistors, except for the source/drain contacts being replaced by superconductors. Similarly, the super current due to proximity effect is tunable by the gate voltage. In this study, we examine the feasibility of JJ-FET-based Boolean logic and memory elements for cryogenic computing, in light of recent advances in novel materials and fabrication techniques. Using a two-dimensional ballistic transport JJ-FET model, we implement circuit level simulations for JJ-FET logic gates, and discuss criteria for realizing signal restoration, as well as fanout. We show that the JJ-FET is a promising candidate for very low power, clocked voltage-level dynamic logic at cryogenic temperatures.