# Energy Efficiency Features of the Intel Skylake-SP Processor and Their Impact on Performance

## TL;DR

This paper analyzes the energy efficiency features of the Intel Skylake-SP processor, revealing their effects on performance and power consumption, with implications for HPC system optimization.

## Contribution

It provides an architectural analysis of Skylake-SP's energy efficiency features and their impact on performance, extending insights to future Intel architectures.

## Key findings

- C-state latencies increased over Haswell-EP
- Uncore frequency control has ~10 ms latency
- Data significantly affects power consumption

## Abstract

The overwhelming majority of High Performance Computing (HPC) systems and server infrastructure uses Intel x86 processors. This makes an architectural analysis of these processors relevant for a wide audience of administrators and performance engineers. In this paper, we describe the effects of hardware controlled energy efficiency features for the Intel Skylake-SP processor. Due to the prolonged micro-architecture cycles, which extend the previous Tick-Tock scheme by Intel, our findings will also be relevant for succeeding architectures. The findings of this paper include the following: C-state latencies increased significantly over the Haswell-EP processor generation. The mechanism that controls the uncore frequency has a latency of approximately 10 ms and it is not possible to truly fix the uncore frequency to a specific level. The out-of-order throttling for workloads using 512 bit wide vectors also occurs at low processor frequencies. Data has a significant impact on processor power consumption which causes a large error in energy models relying only on instructions.