A Novel General Compact Model Approach for 7nm Technology Node Circuit Optimization from Device Perspective and Beyond

TL;DR

This paper introduces a new general compact model for 7nm FinFET devices that combines TCAD calibration with statistical methods, enabling efficient, accurate device and circuit optimization beyond traditional physical derivations.

Contribution

The work presents a novel compact modeling approach that simplifies device modeling for advanced nodes, improving accuracy and scalability while reducing complexity compared to existing models.

Findings

Enhanced accuracy and efficiency in device modeling

Improved circuit performance and variation control

Framework applicable to future 5nm and beyond devices

Abstract

This work presents a novel general compact model for 7nm technology node devices like FinFETs. As an extension of previous conventional compact model that based on some less accurate elements including one-dimensional Poisson equation for three-dimensional devices and analytical equations for short channel effects, quantum effects and other physical effects, the general compact model combining few TCAD calibrated compact models with statistical methods can eliminate the tedious physical derivations. The general compact model has the advantages of efficient extraction, high accuracy, strong scaling capability and excellent transfer capability. As a demo application, two key design knobs of FinFET and their multiple impacts on RC control ESD power clamp circuit are systematically evaluated with implementation of the newly proposed general compact model, accounting for device design, circuit performance optimization and variation control. The performance of ESD power clamp can be improved extremely. This framework is also suitable for pathfinding researches on 5nm node gate-all-around devices, like nanowire (NW) FETs, nanosheet (NSH) FETs and beyond.