Cryogenic low power CMOS analog buffer at 4.2K

TL;DR

This paper presents a novel, power-efficient CMOS analog buffer designed for cryogenic temperatures, achieving high driving capability and low power consumption suitable for low-temperature electronics.

Contribution

The paper introduces a new cryogenic CMOS buffer with a differential input stage for improved rail-to-rail tracking and low power operation at 4.2K.

Findings

Achieves a slew rate of +51 V/us and -93 V/us for 10 pF load

Consumes only 79 μW static power at 4.2K

Operates effectively at 1.4 V supply voltage

Abstract

A novel power-efficient analog buffer at liquid helium temperature is proposed. The proposed circuit is based on an input stage consisting of two complementary differential pairs to achieve rail-to-rail level tracking. Results of simulation based on SMIC 0.18um CMOS technology show the high driving capability and low quiescent power consumption at cryogenic temperature. Operating at single 1.4 V supply, the circuit could achieve a slew-rate of +51 V/us and -93 V/us for 10 pF capacitive load. The static power of the circuit is only 79uW.