# Low-power Programmable Processor for Fast Fourier Transform Based on Transport Triggered Architecture

## TL;DR

This paper presents a low-power, software-programmable processor optimized for FFT computations using transport triggered architecture, achieving high energy efficiency and supporting various FFT sizes.

## Contribution

It introduces a novel low-power processor design that compresses FFT kernels into single instructions and uses an energy-efficient instruction loop buffer.

## Key findings

- Supports FFT sizes from 64 to 16384
- Performs 20916 transforms of size 1024 on 1 mJ
- Energy efficiency comparable to fixed-function implementations

## Abstract

This paper describes a low-power processor tailored for fast Fourier transform computations where transport triggering template is exploited. The processor is software-programmable while retaining an energy-efficiency comparable to existing fixed-function implementations. The power savings are achieved by compressing the computation kernel into one instruction word. The word is stored in an instruction loop buffer, which is more power-efficient than regular instruction memory storage. The processor supports all power-of-two FFT sizes from 64 to 16384 and given 1 mJ of energy, it can compute 20916 transforms of size 1024.