Reconfigurable Hardware Implementation of the Successive Overrelaxation Method

TL;DR

This paper explores implementing the Successive Overrelaxation (SOR) method on reconfigurable FPGA hardware using Handel-C, analyzing performance and feasibility compared to traditional software implementations.

Contribution

It demonstrates the feasibility of hardware implementation of SOR on FPGAs using high-level design tools and compares hardware timing results with software benchmarks.

Findings

Hardware implementation achieves competitive timing performance.

Reconfigurable hardware offers a viable platform for iterative numerical methods.

Comparison shows potential advantages over software execution in specific scenarios.

Abstract

In this chapter, we study the feasibility of implementing SOR in reconfigurable hardware. We use Handel-C, a higher level design tool, to code our design, which is analyzed, synthesized, and placed and routed using the FPGAs proprietary software (DK Design Suite, Xilinx ISE 8.1i, and Quartus II 5.1). We target Virtex II Pro, Altera Stratix, and Spartan3L, which is embedded in the RC10 FPGA-based system from Celoxica. We report our timing results when targeting Virtex II Pro and compare them to software version results written in C++ and running on a general purpose processor (GPP).