Indicating Asynchronous Array Multipliers
P Balasubramanian, D L Maskell

TL;DR
This paper explores the physical implementation of indicating asynchronous array multipliers using CMOS technology, focusing on their robustness, power efficiency, and optimized handshake protocols for 4x4 and 8x8 multiplications.
Contribution
It presents a detailed design and analysis of indicating asynchronous array multipliers with optimized handshake protocols and demonstrates their advantages in power and cycle time reduction.
Findings
Weak-indication array multipliers reduce cycle time and power consumption.
4-phase RTO handshake protocol outperforms RTZ in design metrics.
Biased weak-indication full adder improves overall multiplier efficiency.
Abstract
Multiplication is an important arithmetic operation that is frequently encountered in microprocessing and digital signal processing applications, and multiplication is physically realized using a multiplier. This paper discusses the physical implementation of many indicating asynchronous array multipliers, which are inherently elastic and modular and are robust to timing, process and parametric variations. We consider the physical realization of many indicating asynchronous array multipliers using a 32/28nm CMOS technology. The weak-indication array multipliers comprise strong-indication or weak-indication full adders, and strong-indication 2-input AND functions to realize the partial products. The multipliers were synthesized in a semi-custom ASIC design style using standard library cells including a custom-designed 2-input C-element. 4x4 and 8x8 multiplication operations were…
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Taxonomy
TopicsLow-power high-performance VLSI design · Radiation Effects in Electronics · Analog and Mixed-Signal Circuit Design
