RF Chain Reduction for MIMO Systems: A Hardware Prototype

TL;DR

This paper presents a hardware prototype for RF chain reduction in MIMO systems using hybrid analog combining, demonstrating near-optimal channel estimation performance with fewer RF chains.

Contribution

It introduces a hardware implementation of hybrid RF combining for MIMO, including an optimal design and experimental validation of channel estimation accuracy.

Findings

Hardware prototype achieves near-optimal channel estimation.

Analog combining reduces RF chains cost-effectively.

Experimental results show minimal performance gap from full RF chain systems.

Abstract

Radio frequency (RF) chain circuits play a major role in digital receiver architectures, allowing passband communication signals to be processed in baseband. When operating at high frequencies, these circuits tend to be costly. This increased cost imposes a major limitation on future multiple-input multiple-output (MIMO) communication technologies. A common approach to mitigate the increased cost is to utilize hybrid architectures, in which the received signal is combined in analog into a lower dimension, thus reducing the number of RF chains. In this work we study the design and hardware implementation of hybrid architectures via minimizing channel estimation error. We first derive the optimal solution for complex-gain combiners and propose an alternating optimization algorithm for phase-shifter combiners. We then present a hardware prototype implementing analog combining for RF chain reduction. The prototype consists of a specially designed configurable combining board as well as a dedicated experimental setup. Our hardware prototype allows evaluating the effect of analog combining in MIMO systems using actual communication signals. The experimental study, which focuses on channel estimation accuracy in MIMO channels, demonstrates that using the proposed prototype, the achievable channel estimation performance is within a small gap in a statistical sense from that obtained using a costly receiver in which each antenna is connected to a dedicated RF chain.

Figures

Tables

Table 1. TABLE I: Controllable parameters supported by GUI

Working mode	Simulation		Hardware
Curve display mode	NMSE vs. SNR	NMSE vs. $N_{rf}$	NMSE vs. SNR
Number of UTs	$K=1,\dots ,10$
Number of training symbols	$\tau =1\times K$, $\tau =2\times K$, $\tau =3\times K$
Number of receiving antennas in the BS	$N_{bs}=4$, $N_{bs}=8$, $N_{bs}=16$
Number of RF chains in the BS	$\frac{N_{bs}}{2}$	$2,\dots ,N_{bs}$	$\frac{N_{bs}}{2}$
Rank of receive side correlation matrix	Regular case: , Best case: $rank=N_{rf}$

Equations

$$\mathbf{Y}=\mathbf{WH}{\mathbf{S}}^T+\mathbf{WN},$$

$${\mathbf{W}}^o=\underset{\mathbf{W}\in \mathcal{W}}{\mathrm{argmin}}\text{mathds}E\left\{{\Vert \mathbf{H}-\text{mathds}E\{\mathbf{H}|\mathbf{Y}\}\Vert }_F^2\right\}.$$

$$\mathbf{H}={\mathbf{Q}}^{\frac{1}{2}}\bar{\mathbf{H}}{\mathbf{P}}^{\frac{1}{2}},$$

$$\mathbf{y}$$

$$\hat{\mathbf{h}}$$

$$\times {\left[\left(\mathbf{SP}{\mathbf{S}}^{\ast }\otimes \mathbf{WQ}{\mathbf{W}}^{\ast }\right)+p_n\left({\mathbf{I}}_{\tau }\otimes \mathbf{W}{\mathbf{W}}^{\ast }\right)\right]}^{-1}\mathbf{y}.$$

$$\displaystyle\epsilon=tr\left(\mathbf{P}\otimes\mathbf{Q}\right)-tr\Big{(}\left(\mathbf{P}\mathbf{S}^{*}\otimes\mathbf{Q}\mathbf{W}^{*}\right)\big{.}\Big{.}$$

$$\displaystyle\Big{.}\big{.}\big{[}\left(\mathbf{S}\mathbf{P}\mathbf{S}^{*}\otimes\mathbf{W}\mathbf{Q}\mathbf{W}^{*}\right)+p_{n}\left(\mathbf{I}_{\tau}\otimes\mathbf{W}\mathbf{W}^{*}\right)\big{]}^{-1}\left(\mathbf{S}\mathbf{P}^{*}\otimes\mathbf{W}\mathbf{Q}^{*}\right)\Big{)}.$$

$${\mathbf{W}}^o=\underset{\mathbf{W}\in \mathcal{W}}{\mathrm{argmax}}f(\mathbf{W})$$

$$f(\mathbf{W})$$

$$\displaystyle+\Big{.}\big{.}p_{n}\left(\mathbf{I}_{\tau}\otimes\mathbf{W}\mathbf{W}^{*}\right)\big{]}^{-1}\left(\mathbf{S}\mathbf{P}^{*}\otimes\mathbf{W}\mathbf{Q}^{*}\right)\Big{)}.$$

$$\bar{\mathbf{Q}}\triangleq {\left(\alpha \mathbf{Q}+p_n{\mathbf{I}}_{N_{bs}}\right)}^{-\frac{1}{2}}(\alpha \mathbf{Q}{)}^2{\left(\alpha \mathbf{Q}+p_n{\mathbf{I}}_{N_{bs}}\right)}^{-\frac{1}{2}}.$$

$$\displaystyle\mathbf{W}^{o}=\mathbf{V}\mathbf{D}\big{(}\mathbf{U}^{o}\big{)}^{*}.$$

$${\mathbf{W}}^{po}=\underset{\mathbf{W}\in \mathcal{W},\mathbf{V}\in \mathcal{U},\mathbf{D}\in \mathcal{D}}{\mathrm{argmin}}$$

$$\tilde{\mathbf{W}}$$

$$\tilde{\mathbf{V}}$$

$$\big{(}\tilde{\mathbf{D}}\big{)}_{l,l}=\max\left(\frac{{\rm Re}\left(\left(\mathbf{W}^{*}\mathbf{V}\right)_{:,l}^{*}\left(\mathbf{U}\right)_{:,l}\right)}{\|\left(\mathbf{U}\right)_{:,l}\|^{2}},\eta\right),$$

$${\mathbf{Y}}_b={\mathbf{W}}_b{\mathbf{X}}_b.$$

$$\displaystyle\left[\begin{array}[]{c}\mathbf{Y}_{b}^{1}\\ \hline\cr\mathbf{Y}_{b}^{2}\end{array}\right]=\left[\begin{array}[]{c|c}\mathbf{W}_{b}^{11}&\mathbf{W}_{b}^{12}\\ \hline\cr\mathbf{W}_{b}^{21}&\mathbf{W}_{b}^{22}\end{array}\right]\left[\begin{array}[]{c}\mathbf{X}_{b}^{1}\\ \hline\cr\mathbf{X}_{b}^{2}\end{array}\right].$$

$$f(\mathbf{W})$$

$$\displaystyle=tr\Big{(}(\mathbf{P}\otimes\mathbf{Q})(\mathbf{S}^{*}\otimes\mathbf{U}\mathbf{\Lambda}^{*})\Big{.}$$

$$\displaystyle\quad\Big{.}\times\left[(\mathbf{S}\otimes\mathbf{\Lambda}\mathbf{U}^{*})((\mathbf{P}\otimes\mathbf{Q})+p_{n}\mathbf{I}_{Kn_{bs}})(\mathbf{S}^{*}\otimes\mathbf{U}\mathbf{\Lambda}^{*})\right]^{-1}\Big{.}$$

$$\displaystyle\qquad\qquad\qquad\qquad\Big{.}\times(\mathbf{S}\otimes\mathbf{\Lambda}\mathbf{U}^{*})(\mathbf{P}\otimes\mathbf{Q})^{*}\Big{)}.$$

$$f(\mathbf{W})$$

$$\displaystyle=tr\Big{(}(\mathbf{P}\otimes\mathbf{Q})(\mathbf{S}^{*}\otimes\tilde{\mathbf{U}})\Big{.}$$

$$\displaystyle\quad\quad\Big{.}\times\left[(\mathbf{S}\otimes\tilde{\mathbf{U}}^{*})((\mathbf{P}\otimes\mathbf{Q})+p_{n}\mathbf{I}_{Kn_{bs}})(\mathbf{S}^{*}\otimes\tilde{\mathbf{U}})\right]^{-1}\Big{.}$$

$$\displaystyle\qquad\qquad\qquad\qquad\Big{.}\times(\mathbf{S}\otimes\tilde{\mathbf{U}}^{*})(\mathbf{P}\otimes\mathbf{Q})^{*}\Big{)}$$

$$\stackrel{(a)}{=}K\cdot tr\left({\tilde{\mathbf{U}}}^{\ast }{\alpha }^2{\mathbf{Q}}^2\tilde{\mathbf{U}}{\left[{\tilde{\mathbf{U}}}^{\ast }\left(\alpha \mathbf{Q}+p_n{\mathbf{I}}_{n_{bs}}\right)\tilde{\mathbf{U}}\right]}^{-1}\right),$$

Full text

I Introduction

Next generation wireless systems are required to meet a growing throughput demand [1]. Two key technologies offer the potential of providing dramatic increase in spectral efficiency. The first scheme equips the cellular base stations with a large number of antennas, realizing a massive multiple-input multiple-output (MIMO) system [2, 3, 4]. The second method explores the millimeter wave frequency band, overcoming the congestion of the conventional spectrum [5]. A major drawback of utilizing these technologies stems from the fact that radio frequency (RF) chain circuits, which allow the passband communication signals to be processed in baseband and are thus an essential component in digital receiver architectures, lead to increased cost and power consumption when operating at high carrier frequencies. This increased cost becomes a major practical bottleneck when implementing MIMO antenna arrays operating at millimeter wave bands in which each antenna is connected to an RF chain.

One of the common approaches to mitigate this increased cost is to utilize fewer RF chains [6, 7, 8], namely, implementing RF chain reduction. This reduction is carried out by introducing additional analog hardware, which most commonly consists of controllable phase shifters and adders [6], typically designed to optimize the achievable rate [7] or the channel estimation accuracy [8]. In such systems, the analog signal observed at the antenna array is combined into a lower dimension digital signal using dedicated hardware [9]. When utilizing such hybrid architectures, the number of RF chains, and hence the number of inputs processed in the digital domain, is smaller than the number of antennas. Receiver designs implementing RF chain reduction using analog combining have been the focus of extensive research in recent years [10, 9, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23]. These previous works include the design of different analog combining structures [9, 13, 14, 15, 20, 21], hybrid architectures with low-resolution analog-to-digital conversion [11, 10, 16, 17, 18, 19, 22], and the integration of dynamic analog combining as part of the physical antenna technology [12]. The theoretical maturity of the concept of MIMO communications with RF chain reduction suggests the need to demonstrate and evaluate the implementation of such systems in hardware, which is the focus of this work.

We present a prototype of a configurable analog combining hardware board. Our analog combiner hardware can realize different RF chain reduction strategies, including complex gain combiners [23, 22], phase shifter networks [13, 9], and antenna selection techniques [18]. The board is designed to experimentally evaluate MIMO communications with RF chain reduction applied to actual up-converted passband signals. Similarly to [24, 25], we design a dedicated analog combiner hardware for experimental purposes. While [25] used RF integrated circuits, focusing on millimeter wave bands, our prototype targets the sub-6 GHz frequency range, as in [24]. The main advantage of our prototype over [24] is in the improved phase resolution, which stems from the usage of dedicated vector multipliers, allowing to more accurately set the phase of the complex coefficients and thus to better test analytically derived analog combiners. While our prototype supports a smaller number of antennas compared to [24], we propose a method for using it to experiment in scenarios with larger number of antennas using a virtual channel extension.

Our main design criteria is the channel estimation accuracy, using an analog combining configuration algorithm which extends and improves upon the method suggested in [13]. The proposed algorithm uses alternating optimization to obtain a suitable analog combining configuration under structure constraints, such as the requirement to utilize unit gain coefficients arising in phase shifter networks. Our method achieved closer feasible approximations of the optimal unconstrained combiner compared to the algorithm of [13] by introducing an additional degree of freedom which is exploited to improve the approximation under structure constraints. While we focus on the task of channel estimation, the proposed prototype can be used to implement analog combiners designed according to alternative objectives, e.g., maximize the achievable rate as in [16], or signal recovery, as suggested in [13].

The proposed hardware prototype, which combines our specially designed analog combiner board with a dedicated experimental hardware setup, demonstrates the feasibility of hybrid architectures in wireless networks. In particular, we show that, using a phase shifter network configured with our analog combiner board and the proposed design algorithm, one can achieve channel estimation accuracy which is within a small gap from that achievable using a MIMO receiver with a complex controllable gain combiner.

The main contributions of the paper are summarized below:

• •

We study the design of analog combiners to maximize channel estimation accuracy. To that aim, we first derive the optimal solution for complex-gain hybrid combiners in the noisy setting, extending the derivation in [14, Sec. IV] which considered noiseless settings. We show that the combiner is not unique, and specializes to that of [14] in the high signal-to-noise ratio (SNR) regime.

• •

Then, we propose an algorithm for designing constrained hybrid beamformers, focusing on the common phase-shifter network architecture [9]. Our method is based on alternating optimization, i.e., joint optimization by iteratively optimizing over one quantity while keeping the other variables fixed extending the previously proposed method of [13]. Our algorithm builds upon the non-uniqueness of the complex-gain solution to find the one which can be best approximated using a feasible combiner setting.

• •

Finally, we present a dedicated hardware prototype operating in the sub-6 GHz band, with configurable complex gains of extremely high phase resolution, allowing reliable comparison of different hybrid architectures using passband signals. The prototype is used for evaluating our method, demonstrating its ability to approach the performance of variable gain combiners using constrained phase shifters.

The rest of this paper is organized as follows: In Section II, we formulate the model for wireless communication with RF chain reduction and present the channel estimation problem. Section III details the algorithm implemented for configuring the analog combiner, and Section IV presents a detailed description of the prototype and its components. Experimental results are given in Section V, and Section VI provides concluding remarks.

Throughout the paper, we use boldface lower-case letters to denote vectors, e.g., ${\mathbf{x}}$, and the $i$th element of ${\mathbf{x}}$ is written as $\left({\mathbf{x}}\right)_{i}$. Boldface upper-case letters are used for matrices, e.g. $\mathbf{M}$, whose $(i,k)$th entry is $(\mathbf{M})_{i,k}$ and $i$th column is $(\mathbf{M})_{:,i}$. We use ${\rm vec}(\cdot)$ to denote the vectorization operator, $\mathbf{I}_{n}$ is the $n\times n$ identity matrix, $\otimes$ is the Kronecker product, $\|\cdot\|$ is the $l_{2}$ norm, $\|\cdot\|_{F}$ is the Frobenius norm, $tr(\cdot)$ is the trace operator, while $(\cdot)^{T}$ and $(\cdot)^{*}$ denote the transpose and complex transpose, respectively. The proper-complex Gaussian distribution is denoted as $\mathcal{CN}$, and $\mathbb{C}$ is the set of complex numbers. The expectation of a random variable $x$ is represented by the operator $\mathds{E}\{x\}$.

II System Model

Our hardware prototype implements RF chain reduction for MIMO receivers. In particular, we design the hybrid architecture to facilitate channel estimation in multi-antenna cellular BSs. To formulate the setup and the design objectives, we first detail the problem formulation in Subsection II-A, after which we present the considered model for the unknown channel in Subsection II-B.

II-A Problem Formulation

Consider a single-cell network in which a BS is equipped with $N_{bs}$ antennas and serves $K$ single-antenna user terminals. We focus on the uplink, namely, the transmission from the UTs to the BS. The BS utilizes an analog combiner, and thus observes the channel output after it has been linearly combined and acquired using $N_{rf}\leq N_{bs}$ RF chains. The analog combiner network is denoted via the matrix $\mathbf{W}\in\mathcal{W}$, where $\mathcal{W}\subseteq\mathbb{C}^{N_{rf}\times N_{bs}}$ represents the feasible set of analog combiners. This set is determined by the specific hardware of the analog combiner, and can represent, e.g., complex gains and phase shifter networks [9, 13].

Let $\mathbf{H}\in\mathbb{C}^{N_{bs}\times K}$ denote the wireless channel matrix and $\mathbf{S}\in\mathbb{C}^{\tau\times K}$ be the transmitted symbols of all the UTs in the cell over $\tau$ time instances. We can express the received baseband (BB) signal via

[TABLE]

where $\mathbf{N}\in\mathbb{C}^{N_{bs}\times\tau}$ represents the additive white Gaussian noise (AWGN) corrupting the channel output, modeled as having i.i.d. zero-mean proper-complex Gaussian entries with variance $p_{n}>0$. The resulting model is illustrated in Fig. 1.

Our hardware prototype implements the analog combining matrix $\mathbf{W}$. In particular, we consider two different feasible sets for the analog combining weights $\mathcal{W}$:

Complex-gain analog combiner (CGAC): such analog combiners can realize any form of analog combining, namely, $\mathcal{W}=\mathbb{C}^{N_{rf}\times N_{bs}}$. This architecture is implemented using a hardware network with controllable gains and phase shifters. 2. 2)

Phase-shifter-only analog combiner (PSOAC): here the elements of the combiner matrix have a fixed unit magnitude. Such analog combiners are implemented using adjustable phase shifters, and thus tend to be less costly and simpler to implement compared to CGACs.

Since we focus on facilitating channel estimation, we design the analog combining hardware to minimize the MSE in recovering the channel matrix $\mathbf{H}$ from the observed channel output $\mathbf{Y}$. We assume that $\mathbf{S}$ represents an a-priori known orthogonal pilot sequence, i.e., that channel estimation is carried out in a pilot-aided fashion, where $\mathbf{S}\mathbf{S}^{*}=\mathbf{I}_{\tau}$ and $\tau\geq K$. The design objective can thus be formulated as

[TABLE]

We emphasize that the proposed approach can also be extended to multiple cells, in which the channel output is corrupted by an additional interference term, as well as to signal recovery scenarios. In signal recovery, the observed output $\mathbf{Y}$ in (1) is used to recover the transmitted symbols $\mathbf{S}$, assuming that knowledge of the channel matrix $\mathbf{H}$ (or a reliable estimate of it) is available.

II-B Channel Model

We consider minimum (MMSE) estimation of the unknown channel matrix $\mathbf{H}$ from the channel output $\mathbf{Y}$. We model the distribution of the channel matrix using the common Kronecker model [26, 27, 28]. Accordingly, the matrix $\mathbf{H}$ can be written as

[TABLE]

where $\mathbf{Q}\in\mathbb{C}^{N_{bs}\times N_{bs}}$ and $\mathbf{P}\in\mathbb{C}^{K\times K}$ are the deterministic non-singular receive side and transmit side correlation matrices, respectively; and $\bar{\mathbf{H}}\in\mathbb{C}^{N_{bs}\times K}$ models Rayleigh fading, i.e., its entries are i.i.d. zero-mean unit variance proper-complex Gaussian random variables. We henceforth assume that the transmit side correlation matrix is a scalar multiple of the identity matrix, i.e., $\mathbf{P}=\alpha\mathbf{I}_{K}$ for some $\alpha>0$, representing the scenario in which the UTs are distributed in the cell in an i.i.d.. manner. The correlation matrices $\mathbf{Q}$ and $\mathbf{P}$ are assumed to be known to the BS, and can be utilized for recovering the unknown channel $\mathbf{H}$, as discussed in the following section.

Our motivation for focusing on the Kronecker model (3) with $\mathbf{P}=\alpha\mathbf{I}_{K}$ stems from the fact that this facilitates deriving the optimal unconstrained CGAC, i.e., the solution to (2) when $\mathcal{W}=\mathbb{C}^{N_{rf}\times N_{bs}}$. Nonetheless, our algorithm for designing PSOACs, detailed in Section III, is not restricted to a specific model and only requires an unconstrained CGAC to approximate. Furthermore, our hardware prototype detailed in Section IV is model independent, and can support any analog combiner configuration.

III Analog Combiner Design Algorithm

We now detail the proposed algorithm for designing the analog combining matrix $\mathbf{W}$ based on the objective (2). Our method improves upon the minimal gap iterative quantization (MaGiQ) algorithm suggested in [13], and consists of two steps: we begin by reformulating the MSE objective as a matrix trace expression, and then show how this objective can be utilized to design the analog combiner.

III-A MSE* Objective*

In order to specialize the MSE objective (2) to our channel model detailed in Subsection II-B, we write the channel input-output relationship (1) in vector form. In particular, it holds from (1) that $\mathbf{y}\triangleq{\rm vec}(\mathbf{Y})$ can be written as

[TABLE]

where $\mathbf{h}\triangleq{\rm vec}(\mathbf{H})\sim\mathcal{CN}(\mathbf{0},\mathbf{P}\otimes\mathbf{Q})$ is the unknown channel in vector form and \mathbf{n}={\rm vec}(\mathbf{N})\sim\mathcal{CN}\big{(}\mathbf{0},p_{n}\mathbf{I}_{N_{bs}\cdot\tau}\big{)} is the additive noise. Since $\mathbf{h}$ and $\mathbf{n}$ are mutually independent, it follows from (4) that $\mathbf{y}$ and $\mathbf{h}$ are jointly Gaussian. Hence, the MMSE estimator is given by the linear MMSE estimator [29, Ch. 8], which can be written as

[TABLE]

Accordingly, the MSE \epsilon\triangleq\mathds{E}\big{\{}\|\mathbf{h}-\hat{\mathbf{h}}\|^{2}\big{\}} is given by [29, Ch. 8.4]

[TABLE]

The MSE (6) is determined by the pilot symbols $\mathbf{S}$, the second order statistical moments of the channel, represented by the correlation matrices $\mathbf{Q},\mathbf{P}$, and the analog combiner $\mathbf{W}$. We next assume that $\mathbf{S}$, $\mathbf{P}$, and $\mathbf{Q}$ are known and seek the optimal combiner $\mathbf{W}$ that minimizes the MSE of (6).

III-B Analog Combiner Design

Minimization of (6) is equivalent to maximization of the second trace term of (6), i.e.,

[TABLE]

where

[TABLE]

Let $\mathcal{U}$ and $\mathcal{D}$ be the sets of unitary ${N_{rf}\times N_{rf}}$ matrices and diagonal ${N_{rf}\times N_{rf}}$ matrices with positive diagonal entries. The analog combiner matrix $\mathbf{W}^{o}$ for unconstrained analog combiners, i.e., $\mathcal{W}=\mathbb{C}^{N_{rf}\times N_{bs}}$, is given in the following theorem:

Theorem 1**.**

Let $\mathbf{U}^{o}$ be an $N_{bs}\times N_{rf}$ matrix whose columns are the $N_{rf}$ eigenvectors of $\bar{\mathbf{Q}}$ corresponding to its $N_{rf}$ largest eigenvalues, where

[TABLE]

Then, for any $\mathbf{V}\in\mathcal{U}$ and $\mathbf{D}\in\mathcal{D}$, the optimization problem (7) is solved by setting

[TABLE]

Proof:

The proof is detailed in Appendix A. ∎

We note that in the high SNR regime, i.e., when $p_{n}\approx 0$, $\mathbf{U}$ in Theorem 1 becomes the first $N_{rf}$ eigenvectors of $\alpha\mathbf{Q}$, coinciding with the derivation in [14, Sec. IV] which assumed a noiseless setup.

The analog combiner in (10) is achievable for any $\mathbf{V}$ and $\mathbf{D}$ using the CGAC architecture, in which each element of the analog combining matrix can be any complex value. For the PSOAC case, the entries of the combiner matrix are restricted to have unit amplitude, a condition which may not be satisfied for a matrix of the form (10). Following [13], we propose to exploit the non-uniqueness of $\mathbf{W}^{o}$ to facilitate its approximation using a feasible PSOAC matrix. In particular, we recover the selection of the non-unique $\mathbf{V}$ and $\mathbf{D}$ for which the resulting $\mathbf{W}^{o}$ can be closely approximated using a feasible $\mathbf{W}$, namely, our design objective is

[TABLE]

In [13, Sec. V], only the non-uniqueness in the unitary $\mathbf{V}$ is exploited, and the diagonal $\mathbf{D}$ is assumed to be the identity matrix $\mathbf{I}_{N_{rf}}$. Consequently, our proposed design criterion generalizes that of MaGiQ [13], and is capable of recovering PSOAC matrices which better approximate the unconstrained MSE minimizing analog combiner compared to MaGiQ [13].

We tackle the optimization problem (11) in an alternating fashion. Our design method is based on the following lemma:

Lemma 1**.**

For any fixed $\mathbf{V}\in\mathcal{U}$ and $\mathbf{D}\in\mathcal{D}$, if $\mathcal{W}$ represents PSOAC matrices then

[TABLE]

Proof:

The lemma directly follows from [12, Lem 2]. ∎

Lemma 1 implies that the optimization problem (11) can be solved using alternating optimization. In particular, we propose to update each of the three matrices $\mathbf{W}$, $\mathbf{V}$, and $\mathbf{D}$ in turn, while fixing the remaining two matrices, and to repeat this process iteratively. Since our objective in (11) is the minimization of the convex Frobenius norm, it follows from [30, Thm. 2] that the convergence of such an alternating approach is guaranteed. The proposed iterative alternating optimization method is summarized in Algorithm 1. For a given $\mathbf{U}^{o}$, MaGiQ [13] can be considered as a special case of the proposed algorithm with $\mathbf{D}$ fixed to the identity matrix, i.e., without step 8. This additional degree of freedom allows our algorithm to obtain close feasible approximations of the unconstrained optimal analog combiner $\mathbf{W}^{o}$, at the cost of the additional computation of the $N_{rf}$ diagonal entries of $\mathbf{D}$ in each iteration via (12c).

The fact that our algorithm obtains a better approximation of $\mathbf{W}^{o}$ compared to MaGiQ also translates to improved channel estimation accuracy, as demonstrated in the following example. Consider a multi-user MIMO system in which a BS equipped with $N_{bs}=80$ antennas and $N_{rf}=20$ RF chains serves $K=40$ UTs. The receive side correlation matrix $\mathbf{Q}$ follows the Jakes’ model with antenna spacing of $0.2$ carrier wavelength [31], and the transmit side correlation $\mathbf{P}$ is set to $\mathbf{I}_{K}$. In Fig. 2 we evaluate the normalized MSE, defined as \frac{\epsilon}{\mathds{E}\big{\{}\|\mathbf{h}\|^{2}\big{\}}}, versus SNR, given by ${\rm SNR}=p^{-1}_{n}$. The normalized MSEs are computed using the unconstrained CGAC $\mathbf{W}^{o}$ as well as PSOACs designed using MaGiQ and the proposed algorithm, respectively. Observing Fig. 2 we note that the PSOAC designed using the proposed algorithm achieves effectively the same performance as the CGAC $\mathbf{W}^{o}$ which requires controllable gains, while the normalized MSE achieved using MaGiQ is within a small gap from $\mathbf{W}^{o}$. This small gap in normalized MSE can lead to substantial gaps in MSE, particularly when the Frobenius norm of the channel, \mathds{E}\big{\{}\|\mathbf{h}\|^{2}\big{\}}, is large, as common in massive MIMO systems. This numerical study demonstrates the superiority of the proposed algorithm over previous PSOAC design methods. Consequently, our hardware prototype and its experimental system use Algorithm 1 when realizing PSOACs.

In our prototype we implement both CGACs, designed via (10) by setting $\mathbf{V}=\mathbf{D}=\mathbf{I}_{N_{rf}}$, and PSOACs, configured using Algorithm 1. The architecture of the prototype, which allows it to implement the aforementioned hybrid design in a dynamic manner, is discussed in the following section.

IV System Architecture

In this section, we elaborate on the system architecture of the hardware prototype which realizes the RF chain reduction scheme detailed in the previous section. To that aim, we first present the high-level system architecture in Subsection IV-A, after which we discuss the concrete structure of each of the hardware components in Subsection IV-B.

IV-A High-Level Design

IV-A1 Experimental Environment

Our hardware prototype implements a configurable analog combiner, which is evaluated using a dedicated experimental setup at microwave frequencies. This setup consists of a Matlab-based host application and a field-programmable gate array (FPGA) board. The former simulates the BB channel output and processes the signal captured after analog combining. The latter acts as an interface between the digital signals generated and processed by the host application, and the analog signals which are utilized by the analog combiner hardware. In particular, the input and output signals of the analog combiner hardware are generated as follows:

• •

Analog combiner input: The digital baseband channel outputs simulated by the host application are transferred by an Ethernet cable from the host application to the FPGA board in real-time. The FPGA board generates the baseband input signal which is up-converted on the combiner board using a carrier waveform generated by a VSG25A vector signal generator. The resulting analog passband signal represents the multivariate channel output observed at the BS antenna array.

• •

Analog combiner output: The analog combined passband signal, representing the signal fed to the RF chains at the BS, is down-converted with the same carrier waveform as for the up-conversion on the combiner board, followed by an analog-to-digital conversion implemented on the FPGA. These digital outputs are transferred from the FPGA board to the host application where they are utilized for estimating the underlying channel.

The host application is also capable of adjusting the weights of the analog combining hardware via the FPGA board. The experimental procedure is illustrated in the flow chart at the top of Fig. 3.

IV-A2 Analog combiner implementation

Several different architectures for analog combiners can be found in the literature [9, 13]: The most common is arguably a controllable network of fully connected phase shifters, i.e., the PSOAC. Alternative architectures include fully connected complex gain networks, such as the CGAC; fully connected phase shifters and switches network, and flexible partially connected phase shifters network with sub arrays. We refer the readers to [9, Sec. II] for a detailed account of these analog combining architectures. In order to incorporate a large family of architectures, our analog combiner hardware consists of a controllable network of gains and phase shifters. The outputs of the adjustable gains and phase shifters are then summed by a combiner and fed to an RF chain. In particular, our hardware system consists of 4 input ports and 2 output ports, namely, it can be utilized in a BS with 4 antennas and 2 RF chains. This setup can also be used for experimenting with analog combiners with larger number of antennas and RF chains using a virtual channel extension.

By using the flexible and controllable network of gains and phase shifters, we implement the proposed designs for both CGACs as well as PSOACs. The baseline is to use the hardware board which models a MIMO BS with 4 antenna inputs and 2 RF chains. While this combiner implements a hybrid MIMO receiver with $N_{bs}=4$ and $N_{rf}=2$, it can also be used, along with the experimental setup detailed in the sequel, to evaluate in hardware hybrid MIMO BS with 8 antenna inputs and 4 RF chains as well as 16 antenna inputs and 8 RF chains. The ability to use the board and the experimental setup to evaluate hybrid receivers with larger number of antennas and RF chains is obtained using a virtual channel extension. This virtual channel approach is based on a sequential utilization of the basic hardware to obtain an overall combined result.

To present the virtual channel extension, we note that the two outputs of the analog combiner are obtained as a linear combination of four antenna inputs with different weights, which are determined by some basic combining matrix $\mathbf{W}_{b}$. Defining $\mathbf{X}_{b}\triangleq\mathbf{H}\mathbf{S}^{T}+\mathbf{N}$, we denote the channel output with this basic combining as

[TABLE]

In order to simulate more antenna inputs and RF chains, we utilize multiple time instances to form a single analog combining input-output pair. For example, in order to realize 8 antenna inputs and 4 RF chain, we use two different $4\times 1$ channel output vectors, denoted $\mathbf{X}_{b}^{1}$ and $\mathbf{X}_{b}^{2}$, and four $4\times 2$ analog combining matrices $\mathbf{W}_{b}^{11},\mathbf{W}_{b}^{21},\mathbf{W}_{b}^{12},\mathbf{W}_{b}^{22}$. Now, following (13) we can obtain a configurable $8\times 4$ analog combiner via the assignment

[TABLE]

It follows from (20) that we need to sequentially utilize the basic hardware four times to complete the divided four blocks of the analog combiner matrix. Following the same approach as the realization of 8 antenna inputs and 4 RF chains, a setup with 16 antenna inputs and 8 RF chains can be obtained by utilizing 16 different $4\times 2$ basic combiners to complete the divided 16 blocks of the analog combiner matrix. Clearly, analog combiners with different analog combining ratios, namely, in which the number of antennas is not twice the number of RF chains, can be realized following the same guidelines by using only the required number of input and output ports.

IV-B Prototype Physical Entities

The overall prototype system is depicted at the bottom of Fig. 3. The prototype consists of the following components: a controller and display, providing the GUI, a computing center running the Matlab-based host application, an FPGA board, and the analog combiner hardware. In the following we elaborate on each of these blocks.

IV-B1 Controller and display

The GUI allows to configure and evaluate the experimental setup in a user-friendly environment. In particular, our GUI provides the ability to change the main parameters of the experiment and to numerically compare the normalized MSEs obtained in two display modes: with respect to SNR or number of RF chains. The main controllable parameters include the number of UTs, training symbols, receive antennas, and the rank of the receive side correlation matrix. Details of the supported parameter combinations are summarized in Table I.

Once the experimental setup is configured and a test is launched, the GUI presents in real-time the selected values used to configure the analog combining hardware for both PSOAC as well as CGAC. Furthermore, the GUI presents updated normalized MSE curves during the test and after it is concluded, comparing the performance of the utilized PSOAC and CGAC to analog combiners in which the RF chains are directly connected to randomly selected antennas, as well as to a fully-digital setup. The fully-digital setup, representing the performance achievable without analog combining when each antenna feeds a dedicated RF chain, constitutes a fundamental lower bound on the channel estimation MSE with RF chain reduction. An overview of the GUI is depicted in Fig. 4.

IV-B2 Computing Center

The computing center is a 64-bit laptop with 4 CPU cores and 16GB RAM running the Matlab-based host application. The application is controlled by the GUI, and implements the following functionalities:

• •

The host application computes the analog combiner weights using the algorithm detailed in Section III, and adjusts the analog combiner hardware before each simulation test.

• •

The application generates the digital baseband signals, i.e., the pilot sequences, as well as the wireless channel outputs, which are fed to the FPGA to generate the analog combiner input.

• •

On the receive side, the application processes the baseband channel outputs and produces the MMSE channel estimate via (5).

The communication between the computing center and the hardware board is carried out over an Ethernet cable. Through the cable, the generated digital baseband channel outputs and analog combiner matrix are transmitted to the build-in memory of the FPGA board, and the baseband RF chain outputs are acquired.

IV-B3 FPGA board

The FPGA board consists of an off-the-shelf Xilinx VC707 evaluation board. The evaluation board utilizes a 4DSP FMC204 16-bit DAC mezzanine card for baseband waveform generation, as well as an eight-channel 4DSP FMC168 16-bit digitizer card for sampling of the combined analog signal.

In the baseband analog signal generation process, the waveforms are stored as digital baseband I/Q pairs on the build-in memory. Then, the FPGA device reads out the pre-stored waveforms from the memory and employs an $8$ Gbps Serializer/Deserializer (SerDes) device to transfer it to the $16$-bit DAC mezzanine card. The DAC card then interpolates and converts the stored waveforms to analog baseband signals at a sample rate of $250$ Msps. The analog baseband signals are transmitted to the analog combiner board through coaxial cables where they are up-converted to passband and linearly combined.

The analog combiner outputs, which are down-converted to baseband on the combiner board, are digitized using four out of eight channels of the $16$-bit digitizer card with a $250$ MHz sampling rate. Each I/Q pair occupies two channels of the digitizer card. The $1.2$ Gbps SerDes transfers the sampled data to the FPGA who then writes the data to a digital first-in-first-out (FIFO) buffer for reading by the computing center.

The FPGA also produces selection and control commands for configuring of analog combiner. Once the host application produces an analog combiner configuration, the weights matrix is provided to the FPGA board via the FIFO buffer. These weights are then transferred to the analog combiner hardware using a serial peripheral interface (SPI) protocol, which is used to control the dedicated analog combiner board.

IV-B4 Analog combiner board

The analog combiner board is a self-designed dedicated hardware, which realizes a controllable analog combiner network, and can serve as any of the common combiner architectures, e.g., phase shifter networks, switching networks [13] and DFT beamforming [21]. The designed analog combiner supports two different types of input signals: one is passband signals in the frequency band up to $4.5$ GHz and another is BB signals each with a $125$ MHz maximum bandwidth. In our experimental setup we use BB signals as our inputs, where up-conversion and down-conversion are carried out on the analog combiner board. The board consists of five different blocks, implementing the main different functionalities, namely:

1. C1

Up-conversion of incoming signal and signal splitting. 2. C2

Passband signal input and amplification. 3. C3

Weights (phases and gains) application and configuration. 4. C4

Summing up of the incoming signals. 5. C5

Down-conversion and low-pass filtering of combined signals.

The individual blocks of the analog combiner board are marked in Fig. 5, which depicts the block diagram of the hardware as well as the circuit board.

In block C1, each of the four inputs is a complex BB signal transmitted from the FPGA, feeding an amplifier followed by a mixer. The BB signals whose maximal range of frequency is $125$ MHz are up-converted to RF signals at a frequency of $1$ GHz. The RF signals represent the passband signals observed by the BS antennas and each power level of the RF signals are tuned to [math] dBm and split into two same signals. In order to support passband inputs, one must only replace block C1 with the corresponding passband signals observed by the antennas.

Each of the passband signals is forwarded to block C2, where it is fed to an amplifier with $16$ dB fixed gain. Specifically, we use an ADL5566 dual RF operational amplifier for each splitted pair of passband signals. This amplifier has a low latency and a very flat frequency response, including a channel-to-channel gain and phase errors of $0.1$ dB and $0.06$ degree, respectively, at $100$ MHz. Furthermore, the ADL5566 supports input signals with up to $4.5$ GHz bandwidth without having the amplification vary over frequency, while hardly affecting the SNR due to its low noise input stage of only $1.3nV/\sqrt{Hz}$. Thus, the receiver contains four ADL5566 amplifiers for the four RF input signals. The wideband range property of ADL5566 makes our hardware suitable for a broad range of RF signals used in actual communication systems.

The signals from the amplifiers are separated into two groups. Each group has four inputs, including one signal from each splitted pair. Then, each signal is splitter again into two signals with $90$-degree offset, which are used as the inputs to a phase shifter and gain block. The purpose of this additional splitting with phase offset stems from the fact that we use differential phase shifters which operate on such inputs. In block C3, each of the four channels in one of the groups is activated by an ADL5390 analog vector multiplier, implementing the phase and gain of each analog combining weight applied to the input signal. The weights applied in the vector multiplications are determined by the output DC level of an AD7808 octal 10-bit DACs with serial load capabilities, which receives control commands from the FPGA board used to configure the analog combining weights by finding a look-up table. The usage of controllable gains and phases requires a calibration stage when the interconnections are established to guarantee that the configured weights are correctly translated into the desired phase and gain values.

Arguably, the most common analog combiner architecture is based on phase shifters [9, 16, 17]. In practice, applied phase shifters are digitally controlled with phase resolutions typically above $5$ degrees. This crude resolution may significantly degrade the system performance by inducing quantization errors. In our novel combiner prototype, we used vector multiplexer ADL5390 as an analog phase shifter controlled by the 10-bit DAC, allowing to realize combiner with controllable gains as well as providing the ability to reach an improved resolution of less than $1.5$ degree in phase.

The outputs of each group are summed in block C4, which finalizes the realization process of analog combining and obtains a combined passband signal. Then, the combined signals are down-converted in block C5 using a set of ADL5382 down-converters with the same local oscillator used for up-conversion. The down-converted signals are filtered to baseband signals with a maximum $125$ MHz bandwidth. Finally, the signals of the two outputs are forwarded to the FPGA where they are acquired using a 4DSP FMC168 $16$-bit digitizer card, obtaining the digital outputs for further digital signal processing in the computing center.

V Experiment Results

In the experimental study, we evaluate the channel estimation performance when the observed channel output is combined using our analog combining hardware, configured as both a CGAC as well as a PSOAC. While we focus here on MSE channel estimation, the proposed analog combiner can be used to evaluate various other measures, such as bit error rate, by using different processing of the combiner output, e.g., symbol detection, in the digital domain. We implement CGACs, designed via (10) by setting $\mathbf{V}=\mathbf{D}=\mathbf{I}_{N_{rf}}$, and PSOACs, configured using Algorithm 1. The channel estimation accuracy is compared to that achievable when using a random antenna selection, which randomly selects $N_{rf}$ out of $N_{bs}$ antennas, and also to the traditional fully-digital setup, where each antenna is connected to a dedicated RF chain.

In all the presented experiments, the number of UTs is fixed to $K=3$, and the pilot sequence length is $\tau=K=3$. Following [14], we fix the transmit side correlation matrix $\mathbf{P}$ to the $K\times K$ identity matrix. The receive side correlation matrix $\mathbf{Q}$ is generated as follows: for a fixed $N_{Q}>0$, we randomize an $N_{bs}\times N_{Q}$ proper-complex Gaussian matrix with i.i.d. zero-mean unit variance entries, denoted $\tilde{\mathbf{Q}}$, and set $\mathbf{Q}=\tilde{\mathbf{Q}}\tilde{\mathbf{Q}}^{*}$. We consider two settings of $N_{Q}$: $N_{rf}<N_{Q}\leq N_{bs}$, referred to as the regular setting, and $N_{Q}=N_{rf}$, referred to as the best setting. We generate 1000 independent realizations of $\mathbf{Q}$. It is noted that the general clustered channel model [32, 33] is a special case of our Kronecker channel model used here [13]. The performance metric is the normalized MSE $\frac{\|\mathbf{h}-\hat{\mathbf{h}}\|^{2}}{\|\mathbf{h}\|^{2}}$ over the generated receiver correlation matrices. For each Monte Carlo simulation, new realizations of the channel matrix, noise vector, and pilots matrix are generated. Such noise vector and channel matrix obey the model detailed in Section IV. The pilots matrices are obtained from $K$ eigenvectors of a $\tau\times\tau$ random matrix randomized from a proper-complex Gaussian distribution with i.i.d. zero-mean unit variance entries.

V-A Normalized MSE versus SNR

We first test the normalized MSE in estimating the channel versus SNR in the range $[0,30]$ dB, for an analog combiner with $N_{bs}=8$ antennas and $N_{rf}=4$ RF chains. Note that this analog combiner model is obtained using the virtual channel extension approach detailed in Section IV. The results are depicted in Figs. 6(a)-6(b) for high rank (regular) receive correlation and for low rank (best) receive correlation, respectively. Observing Figs. 6(a)-6(b), we note that using the proposed hardware prototype, the PSOAC configured via Algorithm 1, which represents a practical family of analog combiners, achieves channel estimation accuracy within a very small gap compared to the costly CGAC architecture. Furthermore, both PSOAC and CGAC architectures notably outperform the random antenna selection approach. It is noted however that random antenna selection is simpler to implement compared to analog-combiner based systems, which require additional hardware. As expected, the fully-digital architecture achieves the lowest MSE performance, as it has access to the observed channel output without dimensionality reduction.

For the high rank (regular) receiver correlation case, it is seen in Fig. 6(b) that all approaches which implement analog combining meet an error floor at high SNRs (above $20$ dB). This error floor is due to the model mismatch induced by the dimensionality reduction, which becomes the main performance bottleneck at this SNR regime. However, when the rank of the receive correlation matrix is not larger than the number of RF chains, the optimal MSE performance observed using fully-digital receivers is also achievable using our analog combiner prototype, in line with the theoretical results of [13].

V-B Normalized MSE versus Number of RF Chains

Next, we numerically evaluate the normalized MSE performance achievable using our hardware analog combiner prototype for different numbers of RF chains. Here, we let the number of RF chains $N_{rf}$ vary in the range of $[2,N_{bs}]$, for a fixed SNR level of 15 dB, and for a high rank (regular) receive correlation setup. The results of this experiment are depicted in Figs. 6(c), 6(d) and 6(e), for $N_{bs}=\{4,8,16\}$, respectively. Observing Figs. 6(c)-6(e), we note that for all considered scenarios the normalized MSEs of our hybrid architectures approach the normalized MSEs of the fully-digital receiver as the number of RF chains increases. This result settles with the fact that for $N_{rf}=N_{bs}$ these networks implement a fully-digital receiver. When the reduction rate $\frac{N_{rf}}{N_{bs}}$ is above $62.5\%$, the performance gaps between the proposed analog combiners and the fully-digital receiver become negligible. This behavior is due to the numerical observation that most simulated channels can be reliably characterized by roughly $5/8$ of their eigenmodes, which are reliably recovered and restored using our analog combiner hardware prototype. Moreover, among the hybrid receivers, the PSOAC achieves normalized MSE values which are only slightly higher than that of the costly CGAC, emphasizing the benefits of its design via Algorithm 1. Finally, both the CGAC as well as the PSOAC have lower normalized MSEs than the random antenna selection.

These results demonstrate the ability of our proposed configurable analog combiner hardware to efficiently implement desirable RF chain reduction while inducing minimal performance degradation on the overall communication system.

VI Conclusions

In this work, we presented a hardware prototype of a MIMO receiver with RF chain reduction via configurable analog combining. Our proposed prototype consists of a specially designed combiner board as well as a dedicated experimental setup which allows to test and adjust the analog combiner weights. We configure the analog combiner to optimize the channel estimation accuracy in MIMO systems by proposing an algorithm which improves upon state-of-the art design methods. Using our hardware prototype we were able to achieve MIMO channel estimation accuracy which is comparable to that achievable using costly fully-digital receivers.

Appendix A Proof of Theorem 1

Let $\mathbf{W}=\mathbf{V}\mathbf{\Lambda}\mathbf{U}^{*}$ be the singular value decomposition of $\mathbf{W}$, where $\mathbf{V}\in\mathbb{C}^{N_{rf}\times N_{rf}}$ and $\mathbf{U}\in\mathbb{C}^{N_{bs}\times N_{bs}}$ are its left and right singular matrices, respectively, and $\mathbf{\Lambda}\in\mathbb{C}^{N_{rf}\times N_{bs}}$ is its singular values diagonal matrix. To prove the theorem, we first note that the objective (7) is invariant to the choice of the unitary $\mathbf{V}\in\mathcal{U}$, and thus

[TABLE]

Next, we write $\mathbf{\Lambda}\mathbf{U}^{*}=\tilde{\mathbf{\Lambda}}\tilde{\mathbf{U}}^{*}$ where $\tilde{\mathbf{\Lambda}}\in\mathcal{D}$ and $\tilde{\mathbf{U}}\in\mathbb{C}^{N_{bs}\times N_{rf}}$ are the first $N_{rf}$ columns of $\mathbf{\Lambda}$ and $\mathbf{U}$, respectively. Using this formulation, it is noted that (21) is invariant to the setting of $\tilde{\mathbf{\Lambda}}$, and can be written as

[TABLE]

where $(a)$ follows from the cyclic invariance property of the trace operator and by substituting $\mathbf{P}=\alpha\mathbf{I}_{K}$ and $\mathbf{S}\mathbf{S}^{*}=\mathbf{I}_{\tau}$. The optimization in (22) is then solved using $\tilde{\mathbf{U}}={\mathbf{U}}^{o}$ by [13, Prop. 2], concluding the proof of the theorem. ∎

Acknowledgment

The authors are grateful to Eli Laks, Harel Moalem, Maxim Meltsin, Eli Shoshan, Amir Daichik, and Golan Robinsohn for their help and support in building this prototype.