Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis

TL;DR

This paper introduces a machine learning approach to predict FPGA routing congestion early in high-level synthesis, enabling faster bottleneck identification and design optimization without detailed post-implementation analysis.

Contribution

The paper presents a novel machine learning method for early routing congestion prediction in HLS, mapping congested regions to high-level code for efficient optimization.

Findings

Accurately predicts vertical and horizontal routing congestion with errors of 6.71% and 10.05%.

Enables early bottleneck detection in high-level source code.

Reduces time and effort compared to traditional RTL-based congestion analysis.

Abstract

High-level synthesis (HLS) shortens the development time of hardware designs and enables faster design space exploration at a higher abstraction level. Optimization of complex applications in HLS is challenging due to the effects of implementation issues such as routing congestion. Routing congestion estimation is absent or inaccurate in existing HLS design methods and tools. Early and accurate congestion estimation is of great benefit to guide the optimization in HLS and improve the efficiency of implementation. However, routability, a serious concern in FPGA designs, has been difficult to evaluate in HLS without analyzing post-implementation details after Place and Route. To this end, we propose a novel method to predict routing congestion in HLS using machine learning and map the expected congested regions in the design to the relevant high-level source code. This is greatly beneficial in early identification of routability oriented bottlenecks in the high-level source code without running time-consuming register-transfer level (RTL) implementation flow. Experiments demonstrate that our approach accurately estimates vertical and horizontal routing congestion with errors of 6.71% and 10.05% respectively. By presenting Face Detection application as a case study, we show that by discovering the bottlenecks in high-level source code, routing congestion can be easily and quickly resolved compared to the efforts involved in RTL implementation and design feedback.