# Simulation of Silicon Waveguide Single-Photon Avalanche Detectors for   Integrated Quantum Photonics

**Authors:** Salih Yanikgonul, Victor Leong, Jun Rong Ong, Ching Eng Png, Leonid, Krivitsky

arXiv: 1905.02645 · 2019-10-18

## TL;DR

This paper designs and simulates silicon waveguide SPADs for integrated quantum photonics, demonstrating high detection efficiency, low timing jitter, and dark count rates suitable for chip-scale quantum applications.

## Contribution

It introduces a detailed simulation of silicon waveguide SPADs with different doping profiles, highlighting the superior performance of p-i-n+ configurations for integrated quantum photonics.

## Key findings

- Optimal p-i-n+ SPADs achieve 52.4% PDE at 640 nm
- Timing jitter of 10 ps FWHM demonstrated
- Dark count rate below 5 cps at 243 K

## Abstract

Integrated quantum photonics, which allows for the development and implementation of chip-scale devices, is recognized as a key enabling technology on the road towards scalable quantum networking schemes. However, many state-of-the-art integrated quantum photonics demonstrations still require the coupling of light to external photodetectors. On-chip silicon single-photon avalanche diodes (SPADs) provide a viable solution as they can be seamlessly integrated with photonic components, and operated with high efficiencies and low dark counts at temperatures achievable with thermoelectric cooling. Moreover, they are useful in applications such as LIDAR and low-light imaging. In this paper, we report the design and simulation of silicon waveguide-based SPADs on a silicon-on-insulator platform for visible wavelengths, focusing on two device families with different doping configurations: p-n+ and p-i-n+. We calculate the photon detection efficiency (PDE) and timing jitter at an input wavelength of 640 nm by simulating the avalanche process using a 2D Monte Carlo method, as well as the dark count rate (DCR) at 243 K and 300 K. For our simulated parameters, the optimal p-i-n+ SPADs show the best device performance, with a saturated PDE of 52.4 +/- 0.6% at a reverse bias voltage of 31.5 V, full-width-half-max (FWHM) timing jitter of 10 ps, and a DCR of < 5 counts per second at 243 K.

## Full text

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## Figures

27 figures with captions in the complete paper: https://tomesphere.com/paper/1905.02645/full.md

## References

42 references — full list in the complete paper: https://tomesphere.com/paper/1905.02645/full.md

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Source: https://tomesphere.com/paper/1905.02645