# Interfacing PDM MEMS microphones with PFM spiking systems: Application for Neuromorphic Auditory Sensors

## TL;DR

This paper introduces a low-power, FPGA-based interface converting PDM MEMS microphone signals into spike-based representations for neuromorphic auditory sensors, enhancing speed and efficiency in spike domain processing.

## Contribution

It presents a novel PDM to spike interface (PSI) that improves neuromorphic auditory processing by eliminating traditional analog/digital conversion delays.

## Key findings

- Achieves -39.51dB THD and 59.12dB SNR
- Uses less than 1% FPGA resources
- Consumes below 5mW power

## Abstract

In neuromorphic engineering, computation is commonly performed asynchronously, mimicking the way in which nervous systems process information: spike by spike. The Neuromorphic Auditory Sensor (NAS) has been implemented under this principle: applying different spike-based Signal Processing blocks. Computation in the spike domain requires the conversion of signals from analog or digital representation to the spike domain, which could present a speed constraint in many cases. This paper presents a spike-based system to convert audio information from low-power pulse density modulation (PDM) MicroElectroMechanical Systems (MEMS) microphones into rate coded spike frequencies. These spikes represent the input signal of the NAS, avoiding the analog or digital to spike conversion, and therefore improving the time response of the NAS. This conversion has been done in VHDL as an interface for PDM microphones, converting their pulses into temporal distributed spikes following a pulse frequency modulation (PFM) scheme with an accurate Inter-Spike-Interval, known as "PDM to spikes interface" (PSI). This was tested in two scenarios, first as a stand-alone circuit for its characterization, and then integrated with a NAS for verification. The PSI achieves a Total Harmonic Distortion (THD) of -39.51dB and a Signal-to-Noise Ratio (SNR) of 59.12dB, demands less than 1\% of the resources of a Spartan-6 FPGA and has a power consumption below 5mW.