TS Cache: A Fast Cache with Timing-speculation Mechanism Under Low Supply Voltages

TL;DR

The paper introduces the TS Cache, a novel cache design that uses timing speculation and sense amplifier evaluation to operate reliably and efficiently at low supply voltages, significantly increasing cache frequency.

Contribution

It proposes a timing-speculation mechanism for SRAM caches that detects access errors early, enabling higher frequency operation under low-voltage conditions.

Findings

Achieves 1.62x and 1.92x frequency increases at 0.5V and 0.6V supply voltages.

Demonstrates effectiveness through measurements on fabricated chips.

Improves energy efficiency by enabling reliable low-voltage cache operation.

Abstract

To mitigate the ever-worsening Power Wall problem, more and more applications need to expand their power supply to the wide-voltage range including the near-threshold region. However, the read delay distribution of the SRAM cells under the near-threshold voltage shows a more serious long-tail characteristic than that under the nominal voltage due to the process fluctuation. Such degradation of SRAM delay makes the SRAM-based cache a performance bottleneck of systems as well. To avoid the unreliable data reading, circuit-level studies use larger/more transistors in a bitcell by scarifying chip area and the static power of cache arrays. Architectural studies propose the auxiliary error correction or block disabling/remapping methods in fault-tolerant caches, which worsen both the hit latency and energy efficiency due to the complex accessing logic. This paper proposes the Timing-Speculation (TS) cache to boost the cache frequency and improve energy efficiency under low supply voltages. In the TS cache, the voltage differences of bitlines are continuously evaluated twice by a sense amplifier (SA), and the access timing error can be detected much earlier than that in prior methods. According to the measurement results from the fabricated chips, the TS L1 cache aggressively increases its frequency to 1.62X and 1.92X compared with the conventional scheme at 0.5V and 0.6V supply voltages, respectively.