# Energy-Efficient Runtime Adaptable L1 STT-RAM Cache Design

## TL;DR

This paper introduces LARS, a runtime adaptable STT-RAM cache that dynamically adjusts retention time to optimize energy efficiency across various applications.

## Contribution

LARS is the first cache design allowing dynamic retention time adaptation in STT-RAM, improving energy efficiency with minimal overhead.

## Key findings

- Reduces cache energy by 25.31% on average.
- Supports dynamic retention time adjustment during runtime.
- Maintains minimal overheads in adaptation algorithms.

## Abstract

Much research has shown that applications have variable runtime cache requirements. In the context of the increasingly popular Spin-Transfer Torque RAM (STT-RAM) cache, the retention time, which defines how long the cache can retain a cache block in the absence of power, is one of the most important cache requirements that may vary for different applications. In this paper, we propose a Logically Adaptable Retention Time STT-RAM (LARS) cache that allows the retention time to be dynamically adapted to applications' runtime requirements. LARS cache comprises of multiple STT-RAM units with different retention times, with only one unit being used at a given time. LARS dynamically determines which STT-RAM unit to use during runtime, based on executing applications' needs. As an integral part of LARS, we also explore different algorithms to dynamically determine the best retention time based on different cache design tradeoffs. Our experiments show that by adapting the retention time to different applications' requirements, LARS cache can reduce the average cache energy by 25.31%, compared to prior work, with minimal overheads.