# Integration of Single Photon Emitters in 2D Layered Materials with a Silicon Nitride Photonic Chip

## TL;DR

This paper demonstrates the integration of 2D material-based single photon emitters with silicon nitride photonic chips, enabling efficient, scalable quantum photonic circuits through high-quality coupling and wafer-scale fabrication.

## Contribution

It presents a novel method for integrating monolayer WSe₂ SPEs with SiN chips, coupling with waveguides, and enhancing extraction efficiency via dielectric cavities, advancing scalable quantum photonics.

## Key findings

- Successful coupling of SPEs with SiN waveguides
- Enhanced photon extraction using dielectric cavities
- Compatibility with wafer-scale 2D material growth

## Abstract

Photonic integrated circuits (PICs) enable miniaturization of optical quantum circuits because several optic and electronic functionalities can be added on the same chip. Single photon emitters (SPEs) are central building blocks for such quantum circuits and several approaches have been developed to interface PICs with a host material containing SPEs. SPEs embedded in 2D transition metal dichalcogenides have unique properties that make them particularly appealing as PIC-integrated SPEs. They can be easily interfaced with PICs and stacked together to create complex heterostructures. Since the emitters are embedded in a monolayer there is no total internal reflection, enabling very high light extraction efficiencies without the need of any additional processing to allow efficient single photon transfer between the host and the underlying PIC. Arrays of 2D-based SPEs can moreover be fabricated deterministically through STEM patterning or strain engineering. Finally, 2D materials grown with high wafer-scale uniformity are becoming more readily available, such that they can be matched at the wafer level with underlying PICs. Here we report on the integration of a WSe$_{2}$ monolayer onto a Silicon Nitride (SiN) chip. We demonstrate the coupling of SPEs with the guided mode of a SiN waveguide and study how the on-chip single photon extraction can be maximized by interfacing the 2D-SPE with an integrated dielectric cavity. Our approach allows the use of optimized PIC platforms without the need for additional processing in the host material. In combination with improved wafer-scale CVD growth of 2D materials, this approach provides a promising route towards scalable quantum photonic chips.