# Investigating the Dirac operator evaluation with FPGAs

## TL;DR

This paper evaluates the performance of FPGA devices in executing a computationally intensive Lattice QCD code, comparing external and embedded memory modes to determine optimal configurations for high-performance computing.

## Contribution

It provides detailed benchmarks and performance analysis of FPGA-based Lattice QCD computations, highlighting the impact of memory modes and hardware resources.

## Key findings

- FPGA performance varies significantly with memory mode.
- Embedded memory mode can achieve comparable performance to external memory.
- Resource and throughput estimates guide FPGA optimization for HPC.

## Abstract

In recent years the computational capacity of single Field Programmable Gate Arrays (FPGA) devices as well as their versatility has increased significantly. Adding to that the High Level Synthesis frameworks allowing to program such processors in a high level language like C++, makes modern FPGA devices a serious candidate as building blocks of a general purpose High Performance Computing solution. In this contribution we describe benchmarks which we performed using a Lattice QCD code, a highly compute-demanding HPC academic code for elementary particle simulations. We benchmark the performance of a single FPGA device running in two modes: using the external or embedded memory. We discuss both approaches in detail using the Xilinx U250 device and provide estimates for the necessary memory throughput and the minimal amount of resources needed to deliver optimal performance depending on the available hardware platform.