Cyclic Coding Algorithms under MorphoSys Reconfigurable Computing System

TL;DR

This paper evaluates the performance of cyclic coding algorithms, specifically CRC-16 variants, on the MorphoSys reconfigurable computing system, comparing it with other systems through simulation and analysis.

Contribution

It provides a performance analysis of cyclic coding algorithms on MorphoSys RC, highlighting its advantages and disadvantages compared to other systems.

Findings

MorphoSys shows efficiency in executing cyclic coding algorithms.

Comparison reveals strengths and weaknesses of MorphoSys relative to other systems.

Simulation validates the performance results of the algorithms on MorphoSys.

Abstract

This paper introduces reconfigurable computing (RC) and specifically chooses one of the prototypes in this field, MorphoSys (M1) [1 - 5]. The paper addresses the results obtained when using RC in mapping algorithms pertaining to digital coding in relation to previous research [6 - 10]. The chosen algorithms relate to cyclic coding techniques, namely the CCITT CRC-16 and the CRC-16. A performance analysis study of the M1 RC system is also presented to evaluate the efficiency of the algorithm execution on the M1 system. For comparison purposes, three other systems where used to map the same algorithms showing the advantages and disadvantages of each compared with the M1 system. The algorithms were run on the 8x8 RC (reconfigurable) array of the M1 (MorphoSys) system; numerical examples were simulated to validate our results, using the MorphoSys mULATE program, which simulates MorphoSys operations.