# Lattice QCD on upcoming Arm architectures

## TL;DR

This paper explores the potential of Arm's new SVE instruction set for accelerating Lattice QCD computations, discusses key features of SVE, and details its implementation in the Grid framework.

## Contribution

It introduces the integration of Arm's SVE into Lattice QCD simulations, highlighting its potential benefits for future high-performance computing.

## Key findings

- SVE supports vector lengths up to 2048 bits.
- Implementation of SVE in Grid framework demonstrated feasibility.
- Potential for significant performance improvements in Lattice QCD.

## Abstract

Recently Arm introduced a new instruction set called Scalable Vector Extension (SVE), which supports vector lengths up to 2048 bits. While SVE hardware will not be generally available until about 2021, we believe that future SVE-based architectures will have great potential for Lattice QCD. In this contribution we discuss key aspects of SVE and describe how we implemented SVE in the Grid Lattice QCD framework.